A semiconductor device is provided. The device includes an n type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n type layer disposed therein.

A semiconductor device includes an n type layer disposed in a first surface of an n+ type silicon carbide substrate, a first trench and a second trench disposed in the n type layer and spaced apart from each other, a p type region surrounding a lateral surface and a corner of the first trench, an n+ type region disposed on the p type region and the n type layer between the first trench and the second trench, a gate insulating layer disposed in the second trench, a gate electrode disposed on the gate insulating layer, an oxide layer disposed on the gate electrode, a source electrode disposed on the oxide layer and the n+ type region, and disposed in the first trench, and a drain electrode disposed in a second surface of the n+ type silicon carbide substrate, wherein the source electrode contacts the n type layer.

A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm.sup.2.

A trench gate silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device and a fabrication method thereof. A second conductive heavily doped layer at the bottom corner of a trench gate is electrically connected to a second conductive heavily doped layer on another side edge of the trench gate through a layout design, which ensures a ground potential during voltage blocking state. This design protects the insulating layer in the trench gate and the Schottky contact in a junction barrier Schottky (JBS) diode, thereby enhancing device reliability. Moreover, in a diode operating mode, P+ on the left and right sides of the trench gate are connected to a positive potential. When the P+/N? junction is activated, the conductivity modulation can be implemented through hole injection, thereby improving the device's ability to withstand surge current impacts.

A semiconductor device of embodiments includes: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice the thickness of the silicon carbide layer.

A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.

In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n.sup.+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n.sup.+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.