A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

A semiconductor device according to an embodiment includes a conductive region including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta), an n-type first SiC region, a p-type second SiC region provided between the conductive region and the n-type first SiC region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second SiC region, the n-type first SiC region, and the gate electrode.

A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.

A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

A semiconductor device, including: a drift layer of a first conductivity type provided in a semiconductor base; a base layer of a second conductivity type provided in the semiconductor base at a front surface side thereof; a plurality of first trenches provided in the semiconductor base at a front surface side thereof, and having a plurality of first portions extending in a first direction to form a striped pattern; a second trench provided in the semiconductor base at a front surface side thereof, and having a plurality of second portions extending parallel to the first portions; a plurality of gate electrodes respectively provided in the first trenches; and a diode electrode provided in the second trench. The diode electrode includes: a plurality of inner electrodes provided in the second portions, and an outer electrode connecting the inner electrodes and surrounding ends of the first portions in a plan view.

A semiconductor device includes a semiconductor layer having first and second surfaces and including a first semiconductor region of a first type, first and second electrodes, a first insulation region, a first conductive portion electrically connected to the first electrode, a second insulation region, a first control electrode in the second insulation region, a second semiconductor region of the first type between the first and second insulation regions, a second conductive portion adjacent to the second semiconductor region and forming a Schottky junction with the second semiconductor region, a third semiconductor region of a second type on the first semiconductor region, and a fourth semiconductor region of the first type between the third semiconductor region and the first electrode. The third and fourth semiconductor regions are electrically connected to the first electrode.

A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a second electrode, a third electrode, and a fourth electrode. The third electrode is arranged along a boundary between adjacent regions of the plurality of regions. The third electrode is not located at a portion of the boundary most distant to the second electrode. The third electrode faces the second semiconductor layer via an insulating body. The fourth electrode is located on the third semiconductor layer. The fourth electrode is connected to the second semiconductor layer, the third semiconductor layer, and the second electrode. A portion of the fourth electrode located at the most distant portion has a Schottky barrier junction with the first semiconductor layer.

A semiconductor device includes a major element including a first semiconductor region, a first electrode, a second electrode, a first gate electrode, and a first insulating member being positioned between the first gate electrode and the first semiconductor region, a gate driver supplying the gate voltage to the first gate electrode, and a recording element electrically connected with the gate driver. The recording element records, as continuously changing analog data, a number of times that the gate voltage is supplied to the first gate electrode while being enough to switch the major element on.