A semiconductor device includes a semiconductor layer having a first surface and a second surface, a unit cell including a diode region of a first conductivity type formed in a surface layer portion of the first surface of the semiconductor layer, a well region of a second conductivity type formed in the surface layer portion of the first surface of the semiconductor layer along a peripheral edge of the diode region, and a first conductivity type region formed in a surface layer portion of the well region, a gate electrode layer facing the well region and the first conductivity type region through a gate insulating layer and a first surface electrode covering the diode region and the first conductivity type region on the first surface of the semiconductor layer, and forming a Schottky junction with the diode region and an ohmic junction with the first conductivity type region.

According to one embodiment, a semiconductor device includes first to third electrodes, a first semiconductor portion provided between the first and second electrodes, a second semiconductor portion, and a fourth semiconductor portion. The first semiconductor portion includes first to sixth partial regions. The second partial region is aligned with the first partial region in a second direction crossing a first direction from the first electrode to the second electrode. The third partial region is aligned with the first partial region in the first direction. The fourth partial region is aligned with the second partial region in a third direction crossing a plane including the first and second directions. The fifth partial region is aligned with the fourth partial region in the first direction. The sixth partial region is aligned with the second partial region in the first direction and with the fourth partial region in the third direction.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor portion, a second semiconductor portion, a third semiconductor portion, and a fourth semiconductor portion. The first semiconductor portion is of a first conductivity type. The first semiconductor portion includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor portion is of a second conductivity type. The second semiconductor portion includes a first portion, a second portion, a third portion, and a fourth portion. The first portion has a first depth, the second portion has a second depth shallower than the first depth, and the third portion has the first depth. The third semiconductor portion is of the second conductivity type, and includes a first region portion and a second region portion. The fourth semiconductor portion is of the first conductivity type.

A semiconductor device of embodiments includes: a first silicon carbide region of first conductive type including a first region in contact with a first face of a silicon carbide layer having first and second faces; a second silicon carbide region of second conductive type above the first silicon carbide region; a third silicon carbide region of second conductive type above the second silicon carbide region; a fourth silicon carbide region of first conductive type above the second silicon carbide region; a first gate electrode and a second gate electrode extending in the first direction; a first electrode on the first face and including a first portion and a second portion between the first and the second gate electrode. The first portion contacts the third and the fourth silicon carbide region. The second portion provided in the first direction of the first portion and contacts with the first region.

The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

Described herein are semiconductor devices that include an epitaxial silicon carbide drift region with vertical current transport having a rectifying current injector or field effect transistor current injector on the upper portion of the drift layer and a lower portion having a contact on a substrate or contact on a drift layer to collect current.

A semiconductor component includes: gate structures extending into a silicon carbide body from a first surface to a first depth and having a width along a first horizontal direction parallel to the first surface; contact structures extending into the silicon carbide body from the first surface to a second depth, the gate and contact structures alternating along the first horizontal direction; shielding regions which, in the silicon carbide body, adjoin a bottom of the contact structures but not a bottom of the gate structures and are spaced apart from the gate structures along the first horizontal direction; and source regions between the first surface and body regions. The body regions form pn junctions with the source regions and include main sections adjoining the gate structures, and between the main sections and the contact structures, contact sections adjoining the contact structures.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

A semiconductor device according to an embodiment includes: a transistor, the transistor including a first electrode, a second electrode, semiconductor regions provided between the first electrode and the second electrode, and a gate electrode; a detector detecting a voltage of the first electrode or a current flowing from the first electrode to the second electrode in a state where the voltage of the first electrode is a positive voltage higher than a voltage of the second electrode; a comparison circuit comparing a measurement value measured by the detector with a first threshold; and a gate driver circuit applying a first positive voltage higher than a threshold voltage of the transistor to the gate electrode, and applying a first negative voltage to the gate electrode when the measurement value exceeds the first threshold as a result of comparison in the comparison circuit.

A semiconductor device, comprising: a semiconductor substrate, a parallel pn layer formed in the semiconductor substrate; first semiconductor regions selectively provided in the semiconductor substrate and in contact with the parallel pn layer; second semiconductor regions selectively provided in the semiconductor substrate; gate electrodes respectively provided at positions facing the semiconductor substrate across gate insulating films; first and second electrodes respectively provided at first and second main surfaces of the semiconductor substrate; and conductive films selectively provided between the first main surface of the semiconductor substrate and the first electrode, each conductive film being in contact with the first electrode and first-conductivity-type column regions. The conductive films and the first-conductivity-type column regions form Schottky junctions therebetween, configuring a Schottky barrier diode. The parallel pn layer has a first low carrier lifetime region formed at depth positions respectively directly beneath the first semiconductor regions.