A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.

A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.

A method of forming a metal silicide can include depositing an interface layer on exposed silicon regions of a substrate, where the interface layer includes a silicide forming metal and a non-silicide forming element. The method can include depositing a metal oxide layer over the interface layer, where the metal oxide layer includes a second silicide forming metal. The substrate can be subsequently heated to form the metal silicide beneath the interface layer, using silicon from the exposed silicon regions, the first silicide forming metal of the interface layer and the second silicide forming metal of the metal oxide layer.

One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

A method of manufacturing a semiconductor device is provided including forming a gate electrode layer over a semiconductor substrate, forming a sidewall spacer at a sidewall of the gate electrode layer, forming a raised source/drain region over the semiconductor substrate and adjacent to the sidewall spacer, removing a portion of the sidewall spacer, thereby exposing a portion of the sidewall of the gate electrode layer, and forming an electrically conductive layer electrically connecting the exposed portion of the sidewall of the gate electrode layer and the source/drain region.

A method of manufacturing a semiconductor device with a fuse is provided including the steps of providing a semiconductor-on-insulator (SOI) structure including an insulating layer and a semiconductor layer formed on the insulating layer, forming a first raised semiconductor region on the semiconductor layer and a second raised semiconductor region on the semiconductor layer adjacent to the first semiconductor region, and performing a silicidation process of the first and second raised semiconductor regions to form a first at least partially silicided raised semiconductor region with a first silicided portion and a second at least partially silicided raised semiconductor region with a second silicided portion.