An antiferroelectric memory device includes at least one antiferroelectric memory cell. Each of the at least one antiferroelectric memory cell includes a first electrode, a second electrode and a stack containing an antiferroelectric layer and a doped semiconductor layer or a ferroelectric layer located between the first and the second electrodes.

A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

A method (of reading a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes reading the second bit including: applying a gate sub-threshold voltage to the gate terminal; applying a read voltage to the second S/D terminal; applying a do-not-disturb voltage to the first S/D terminal; and sensing a first current at the second S/D terminal; and wherein the read voltage is lower than the do-not-disturb voltage.

3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.

A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes depositing a grid layer over a substrate. The grid layer is patterned to form a grid structure. The grid structure comprises a plurality of sidewalls defining a plurality of openings. A ferroelectric layer is deposited over the substrate. The ferroelectric layer fills the plurality of openings and is disposed along the plurality of sidewalls of the grid structure. An upper conductive structure is formed over the grid structure.