A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an active pillar, where the active pillar includes: a channel region, as well as a first doped region and a second doped region located at two sides of the channel region, the channel region, the first doped region, and the second doped region having a same doping type, where a counter-doped region is arranged in the channel region, the counter-doped region is close to the first doped region, and a doping type of the counter-doped region is different from a doping type of the channel region; and a gate, where the gate surrounds a part of the channel region, and in a plane in which an axis of the active pillar is located, projection of the gate partially overlaps with projection of the counter-doped region.

The present disclosure relates to a semiconductor structure that includes a well region and a semiconductor substrate. The well region is disposed within the semiconductor substrate. The well region includes a plurality of first regions separated by a plurality of second regions, where the plurality of first regions is of a first doping and the plurality of second regions are of a second doping different than the first doping. A gate electrode overlies the well region where the gate electrode is disposed laterally over a portion of the plurality of first regions and a portion of the plurality of second regions.

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

Disclosed are a bidirectional power device and a method for manufacturing the same. The bidirectional power device includes a semiconductor layer, a plurality of trenches located in the semiconductor layer, a gate dielectric layer located on an inner wall of each of the plurality of trenches, a control gate located at a lower portion of each of the plurality of trenches, a shield gate located at an upper portion of each of the plurality of trenches and an isolation layer located between the control gate and the shield gate. When the bidirectional power device is turned off, charges of a source region and a drain region are depleted by the shield gate through a shield dielectric layer, thereby improving voltage withstand property. When the bidirectional power device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.

A transistor and a manufacturing method are provided. The transistor includes at least one gate electrode, a channel, a gate dielectric layer, a source and a drain. The channel is curved. A doping concentration of a first portion of the channel is different from a doping concentration of a second portion of the channel. The gate dielectric layer is disposed between the gate electrode and the channel. The source is connected to the channel. The drain is connected to the channel.

A method of manufacturing a semiconductor device includes: performing a first etching operation to form a first trench in a semiconductor substrate; forming a doped region to on a first sidewall of the first trench; performing a second etching operation on the first trench to form a second trench in the semiconductor substrate; depositing a dielectric material in the first and second trenches to form an isolation structure, wherein the isolation structure defines a channel region of the semiconductor device from a top-view perspective; and depositing a dielectric layer on the semiconductor substrate over the doped region and the channel region.