An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having a top area at a top side, a bottom area at an underside, and side areas connecting the top area and the bottom area; electrical contact locations at the top area or at the bottom area of the optoelectronic semiconductor chip; and an electrically insulating shaped body, wherein the optoelectronic semiconductor chip is a flip-chip having the electrical contract locations only at one side, either the underside or the top side, the shaped body surrounds the optoelectronic semiconductor chip at its side areas, and the shaped body is free of a via that electrically connects the optoelectronic semiconductor chip.

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

At least some embodiments of the present disclosure relate to a lid for covering an optical device. The lid includes a metal member and a transparent encapsulant. The metal member includes a top surface, a first bottom surface, and a second bottom surface between the top surface and the first bottom surface. The transparent encapsulant is surrounded by the metal member and covers at least a portion of the second bottom surface.

High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

Techniques are disclosed for providing an optical sensor that can be used for wind sensing and an optical scope. The optical sensor can include a photodiode, an electrical switch, a trans-impedance amplifier (TIA), and a capacitive trans-impedance amplifier (CTIA), enabling the optical sensor to perform both wind-sensing and range-finding functions. Some embodiments may include some or all of these components in an application-specific integrated circuit (ASIC), depending on desired functionality.

A semiconductor light detection element includes a plurality of avalanche photodiodes operating in Geiger mode and formed in a semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on a first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to a second principal surface side. A mounting substrate includes a plurality of electrodes arranged corresponding to the respective through-hole electrodes on a third principal surface side. The through-hole electrodes and the electrodes are electrically connected through bump electrodes, and a side surface of the semiconductor substrate and a side surface of a glass substrate are flush with each other.

A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.

The present disclosure provides a semiconductor device including: a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.

An optoelectronic component includes at least one inorganic optoelectronically active semiconductor component having an active region that emits or receives light during operation, and a sealing material directly applied by atomic layer deposition, wherein the semiconductor component is applied on a carrier, the carrier includes electrical connection layers, the semiconductor component electrically connects to one of the electrical connection layers via an electrical contact element, and the sealing material completely covers in a hermetically impermeable manner and directly contacts all exposed surfaces including sidewall and bottom surfaces of the semiconductor component and the electrical contact element and all exposed surfaces of the carrier apart from an electrical connection region of the carrier.

A sensor chip package structure and a manufacturing method thereof are provided. The sensor chip package structure includes a substrate, a sensor chip and a wiring layer. The sensor chip is mounted on the substrate and has a top surface and a concave portion concaved from the top surface. The sensor chip has an active region formed on the top surface and the concave portion is located at one side of the active region. The concave portion has a depth of 100 m to 400 m. The wiring layer is disposed on the sensor chip and electrically connected to the active region. At least a portion of the wiring layer extends from the active region along a sidewall of the concave portion to a bottom surface of the concave portion.