The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having side areas covered by a shaped body; at least one via including an electrically conductive material; and at least one electrically conductive connection electrically conductively connected to the semiconductor chip and the via, wherein the via is laterally spaced part from the semiconductor chip; the via includes a contact pin, the contact pin including an electrically conductive material; and the contact pin is laterally completely enclosed by the shaped body.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided on the substrate 1 and spaced apart from each other in a direction x, a light-transmitting resin 4 covering the light-receiving element 3, a light-transmitting resin 5 covering the light-emitting element 2, and a light-shielding resin 6 covering the light-transmitting resin 4 and the light-transmitting resin 5. The wiring pattern 8 includes a first light-blocking portion 83 interposed between the light-shielding resin 6 and the substrate 1 and positioned between the light-receiving element 3 and the light-emitting element 2 as viewed in x-y plane. The first light-blocking portion 83 extends across the light-emitting element 2 as viewed in the direction x.

According to one embodiment, a semiconductor device includes: a first substrate; a first transistor provided on the first substrate; a light receiving element; and a light emitting element provided on the light receiving element, wherein the first substrate, the first transistor, the light emitting element, and the light receiving element are disposed sequentially in a first direction.

The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.

High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

A package for an optical semiconductor device includes an eyelet, a signal lead inserted in a through hole formed in the eyelet, and sealing glass sealing the signal lead in the through hole. The signal lead includes a first portion, a second portion and a third portion that are greater in diameter than the first portion and on opposite sides of the first portion, a first tapered portion extending from the second portion to the first portion, and a second tapered portion extending from the third portion to the first portion. The first portion and the first and second tapered portions are buried in the sealing glass. The total length of a part of the second portion in the sealing glass and a part of the third portion in the sealing glass is 0.2 mm or less.