A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers.

An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.

Photoelectric conversion device incudes first region of first conductivity type arranged in semiconductor layer having first second surfaces, second region of second conductivity type arranged between the second surface and the first region and forming avalanche photodiode, separation region of the second conductivity type arranged between the first and second surfaces to surround the second region, contact region of the second conductivity type contacted to the separation region, first contact plug connected to the first region, and second contact plug connected to the contact region. The second region has shape of rectangle, and the second contact plug is arranged in diagonal direction of the rectangle. Distance between center of the first contact plug and center of the second contact plug is larger than distance between center of the second region and the center of the second contact plug.

An apparatus wherein, in plane view, a first semiconductor region of a first conductivity type overlaps at least a portion of a third semiconductor region, a second semiconductor region overlaps at least a portion of a fourth semiconductor region of a second conductivity type, a height of a potential of the third semiconductor region with respect to an electric charge of the first conductivity type is lower than that of the fourth semiconductor region, and a difference between a height of a potential of the first semiconductor region and that of the third semiconductor region is larger than a difference between a height of a potential of the second semiconductor region and that of the fourth semiconductor region.

Provided is a component arrangement, including a carrier substrate; a spacer which is arranged on the carrier substrate so as to surround an installation space and has an outlet opening on a side facing away from the carrier substrate; an optical component arranged in the installation space; a contact connection which electrically conductively connects the optical component to external contacts arranged outside the installation space; a cover substrate which is arranged on the spacer and with which the outlet opening is covered in a light-permeable manner; and a light-reflecting surface which is formed on an anisotropically etched silicon component and is arranged in the installation space as an inclined surface at an angle of approx. 45 relative to the surface of the carrier substrate facing the installation space, in such a way that light radiated in a horizontal direction onto the light-reflecting surface can be radiated out in the vertical direction through the opening and the cover substrate, and vice versa.

A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate.

The method of a wafer level packaging includes preparing a substrate, assembling a system on a first side of the substrate, and placing solder balls on a second side of the substrate. The soldering balls s fixed on to the second side of the substrate after the module has been assembled.

The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.

A manufacturing method of a sensing integrated circuit including the following acts. A plurality of transistors are formed. At least one dielectric layer is formed on or above the transistors. A plurality of connecting structures are formed in the dielectric layer. The connecting structures are respectively and electrically connected to the transistors. A plurality of separated conductive wells are respectively formed in electrical contact with the connecting structures.

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.