Provided is a method of manufacturing a thin-film transistor substrate, the method includes forming a semiconductor pattern layer on a substrate. A first insulating film is formed on the semiconductor pattern layer. A metal pattern layer including a gate electrode and first and second alignment electrodes respectively spaced apart from two sides of the gate electrode is formed on the first insulating film. A cover layer covering the gate electrode is formed. The first and second alignment electrodes are removed. A first doping process is performed by doping the semiconductor pattern layer with a first impurity by using the cover layer as a mask. The cover layer is removed. A second doping process is performed by doping the semiconductor pattern layer with a second impurity having a lower impurity concentration than the first impurity by using the gate electrode as a mask.

An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.

An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.

An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode.

An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.

A method of fabricating a polycrystalline silicon thin film transistor device includes the following steps. A substrate is provided, and a buffer layer having dopants is formed on the substrate. An amorphous silicon layer is formed on the buffer layer having the dopants. A thermal process is performed to convert the amorphous silicon layer into a polycrystalline silicon layer by means of polycrystalization, and to simultaneously out-diffuse a portion of the dopants in the buffer layer into the polycrystalline silicon layer for adjusting a threshold voltage. The polycrystalline silicon layer is patterned to form an active layer. A gate insulating layer is formed on the active layer. A gate electrode is formed on the gate insulating layer. A source doped region and a drain doped region are formed in the active layer.

An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.

Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.