A method of fabricating an IC includes: forming first and second arrays of active-region structures extending between first and second vertical zone-boundaries, the first vertical zone-boundary being a boundary of a first keep-out zone, and the second vertical zone-boundary being a boundary of a second keep-out zone; forming first-side boundary cells aligned with the first vertical zone-boundary, including: forming a first-side boundary cell that includes: a first ESD device region including a first ESD protection circuit; and a first pick-up region; and forming second-side boundary cells aligned with the second vertical zone-boundary, including: forming a second-side boundary cell that includes: a second ESD device region including a second ESD protection circuit.

An integrated circuit (IC) device includes a substrate, first and second semiconductor devices correspondingly in different first and second doped regions in the substrate. A gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The IC device further includes a first reverse diode electrically coupled between the substrate and a doped well. The doped well is in the first doped region and a source/drain of the first semiconductor device is in the doped well. Alternatively, the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.

An electronic device comprising a substrate, an electronic element, a driving element, a plurality of first traces, a plurality of second traces and an electrostatic discharge protection element is provided. The substrate comprises a first surface and a second surface, wherein the first surface is opposite to the second surface. The electronic element is disposed on the first surface. The driving element is disposed on the second surface. The plurality of first traces are disposed on the first surface. The plurality of second traces are disposed on the second surface and are electrically connected to the driving element. The electrostatic discharge protection element is disposed on the first surface, and is electrically connected to the electronic element, wherein the electrostatic discharge protection element is electrically connected to the driving element through one of the plurality of first traces and one of the plurality of second traces.

The array substrate includes a carrier substrate, a first signal line and an electrostatic protective circuit, the carrier substrate is provided with a display area and a non-display area; the first signal line is located in the non-display area; the electrostatic protective circuit includes a diode ring, the diode ring is located in the non-display area, the diode ring includes a gate pattern layer and a source and drain pattern layer, the source and drain pattern layer is located on the side of the gate pattern layer and the first signal line away from the carrier substrate, the source and drain pattern layer is connected to the first signal line through a first through hole, and the source and drain pattern layer is connected to the gate pattern layer through a second through hole.

A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.

An electro-static protection structure includes a substrate, a transistor formed in the substrate, and a capacitor. A first pole of the transistor is connected with an electro-static terminal, and a second pole of the transistor and a gate electrode of the transistor are connected with a discharge terminal. A first pole of the capacitor is connected with the substrate, and a second pole of the capacitor is connected with the electro-static terminal.

A method for monitoring a switchable semiconductor component having a protective circuit connected in parallel to the semiconductor component includes tapping an electrical variable applied to the semiconductor component and the protective circuit, and detecting damage to the semiconductor component and/or the protective circuit when an electrical variable is greater than a previously known critical value.

A display substrate and a display apparatus are provided. The display substrate includes: a display area and a non-display area located around the display area, wherein the non-display area includes: at least one Electro-Static discharge (ESD) protection unit, each ESD protection unit includes: multiple transistors connected in series, a first electrode of each transistor is connected with a gate, and the multiple transistors are arranged along a first inclination direction, a first preset included angle is provided between the first inclination direction and a first direction, the first preset included angle ranges from 10 to 80, and the first direction is an extending direction of a gate line in the display area.

A semiconductor device is provided and includes a device finger including field effect transistors (FETs) or bipolar junctions arrayed along a substrate and one or more implanted ballasting elements. Each of the one or more implanted ballasting elements contacts a collector or an emitter of one of the FETs or the bipolar junctions and extends substantially horizontally from the collector or the emitter of the one of the FETs or the bipolar junctions and through the substrate.