An electrostatic discharge (ESD) device may include a semiconductor substrate including a first region, a second region, and a device isolation structure. The first region may include a first impurity region having a first conductivity type, a second impurity region having a second conductivity type opposite the first conductivity type, a first base well, and a first well in the first base well. The device isolation structure may be between the first and second impurity regions. The first base well may surround the first impurity region, the second impurity region, and lower portions of the device isolation structure in the substrate. The first well may have the first conductivity type. The first well may be spaced apart from the device isolation structure in a first direction with a portion of the first base well therebetween.

Disclosed herein are IC devices, packages, and device assemblies that include diodes arranged so that their first and second terminals may be contacted from the opposite faces of a support structure. Such diodes are referred to herein as vertical diodes to reflect the fact that the diode extends, in a vertical direction (i.e., in a direction perpendicular to the support structure), between the bottom and the top of support structures. Vertical diodes as described herein may introduce additional degrees of freedom in diode choices in terms of, e.g., high-voltage handling, capacitance modulation, and speed.

An example apparatus includes a data terminal, a first power line supplied with a first voltage, a second power line supplied with a second voltage different from the first voltage, first and second transistors coupled in series between the first power line and the data terminal, a third transistor coupled between the second power line and the data terminal, and a first ESD protection element coupled between the first power line and a first internal node between the first and second transistors.

A semiconductor package includes at least a first die. The first die includes an internal circuit disposed on a substrate, an electrostatic discharge (ESD) protection circuit disposed on the substrate but laterally spaced from the internal circuit and including a first charge dissipation element, and a first Silicon Controlled Rectifier (SCR) laterally adjacent to and spaced from the first charge dissipation element.

Disclosed is a display substrate including a base substrate, at least one first signal line, and multiple signal access pins. The base substrate includes a display region and a peripheral region located at a periphery of the display region. The peripheral region includes a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region which are communicated sequentially. The first signal line is located in the peripheral region and includes at least two sub-signal lines connected with each other. The multiple signal access pins are located in a signal access region. Each sub-signal line of the first signal line extends to the signal access region and is connected with at least one signal access pin in the signal access region so as to be connected with a driver chip through the signal access pin.

A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

A display panel has a display region and a bezel region located on side(s) of the display region. The display panel includes a substrate; a plurality of sub-pixels disposed on a side of the substrate and located in the display region; a mirror layer disposed on a side of the plurality of sub-pixels away from the substrate; and an electrostatic protection portion electrically connected to the mirror layer and located in the bezel region. The electrostatic protection portion is configured to provide electrostatic protection for the mirror layer.

A MOSFET is provided, including a semiconductor body having a first major surface, a trench extending into the body from the first major surface to a gate region, the body including: a source region of a first conductivity type adjacent a sidewall of the trench at the first major surface, a drain region of the first conductivity type adjacent the trench distant from the source region, and a channel-accommodating region of a second conductivity type opposite to the first conductivity type, adjacent the sidewall of the trench between the source region and the drain region. The semiconductor body includes an Electro Static Discharge (ESD) region of the first conductivity type spaced apart from the trench and extending from the first major surface towards, but not into, the drain region. The ESD region includes a first region of the second conductivity type connected to the gate region.

The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.

A light emitting display apparatus includes a substrate, a display portion including a plurality of pixel driving lines disposed over the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light emitting device layer including a self-emitting device disposed at the display portion, a dam disposed along an edge portion of the substrate, the dam including a metal line, an encapsulation layer including an organic encapsulation layer disposed on an encapsulation region surrounded on at least four sides by the dam, and an anti-electrostatic circuit selectively disposed in outermost pixels of the plurality of pixels, wherein the anti-electrostatic circuit is electrically coupled between a pixel driving line of the plurality of pixel driving lines, the pixel driving line being disposed in at least one of the outermost pixels and the metal line disposed in the dam.