A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.

An electronic device is provided, which includes a substrate, a first wire, a second wire, a first semiconductor element, and a second semiconductor element. The first wire is disposed on the substrate and extends along a first direction. The second wire is disposed on the substrate and extends along a second direction different from the first direction. The first semiconductor element is overlapped with the first wire. The second semiconductor element is adjacent to the first semiconductor element. The first semiconductor element has a first portion and a second portion separated from each other along the first direction by a first distance, the second semiconductor element has a third portion and a fourth portion separated from each other along the first direction by a second distance, and the second distance is less than the first distance. The second wire is at least partially overlapped with the second semiconductor element.

A semiconductor integrated circuit device may include a first region, a second region, a pad structure and an electrostatic discharge (ESD) connection. The first region may be positioned adjacent to a semiconductor substrate. An ESD protection circuit may be integrated in the first region. The second region may be stacked on the first region. A plurality of memory cells may be formed in the second region. The pad structure may be arranged over the second region to receive an external voltage. The ESD connection may include a plurality of lower conductive wirings in the first region. At least one of the lower conductive wirings may be electrically connected with the ESD protection circuit. The at least one of the lower conductive wirings may be drawn to a portion corresponding to the pad structure.

According to one embodiment, a semiconductor device includes a semiconductor layer and a diode. The diode is provided on an outer peripheral region of the semiconductor layer via an insulating layer. The diode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region including a first extending portion that extends in a first direction and multiple first protruding portions that protrude from the first extending portion in a second direction. The second semiconductor region includes a second extending portion that extends in the first direction and multiple second protruding portions that protrude from the second extending portion in the second direction. The first protruding portions and the second protruding portions alternate in the first direction.

An electronic device includes a scan line, an active element, an internal short-circuit ring, an electrostatic protection element. The active element is disposed in an active area and electrically connected to the scan line. The internal short-circuit ring is disposed in a peripheral area and surrounds the active area. The electrostatic protection element is disposed in the peripheral area and electrically connected to the internal short-circuit ring and the scan line. The electrostatic protection element is a transistor and includes a gate electrode, first and second source/drain electrodes, and a semiconductor layer. The gate electrode is in a floating state, the first source/drain electrode is coupled to the internal short-circuit ring, the second source/drain electrode is coupled to the scan line. A first parasitic capacitance between the gate electrode and the first source/drain electrode is greater than a second parasitic capacitance between the gate electrode and the second source/drain electrode.

An array substrate has a display area, and includes a base, pixel groups arranged in multiple lines in a first direction, pixel circuit groups arranged in the first direction, and at least one shift register circuit. Each of at least one pixel group includes a plurality of pixels arranged in at least one line. Each pixel includes at least one sub-pixel. Each of at least one pixel circuit group is disposed between two adjacent lines of pixels, each pixel circuit group includes a pixel driving sub-circuit group, and the pixel driving sub-circuit group is configured to supply pixel driving signals to sub-pixels electrically connected to the pixel driving sub-circuit group. A shift register circuit is disposed between two adjacent lines of pixels, and the shift register circuit is configured to supply scan driving signals to at least one pixel driving sub-circuit group electrically connected to the shift register circuit.

An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

A semiconductor device is provided. The semiconductor device comprises a substrate, a transistor and a snubber circuit. The transistor and the snubber circuit are disposed on the same substrate, and are electrically connected. The snubber circuit has a polycrystalline silicon layer and a dielectric layer, which are adjacently arranged and electrically connected in series. The polycrystalline silicon layer is electrically connected to a source of the transistor, and the dielectric layer is electrically connected to a drain of the transistor so that the polycrystalline silicon layer acts as a resistor, the dielectric layer acts as a capacitor and the snubber circuit acts as an RC snubber circuit.

A semiconductor device includes a substrate including a logic cell region and an ESD cell region, a plurality of active fins on the ESD cell region, disposed alternately in a first direction, including first active fins and second active fins disposed alternately and spaced apart in the first direction, a device isolation layer defining the first and second active fins, a pair of source/drain patterns on each of the plurality of active fins, spaced apart from each other in a second direction intersecting the first direction, a channel pattern between the pair of source/drain patterns, and a gate electrode extending in the first direction on the channel pattern, wherein each of the first and second active fins extending in the second direction, and a length of the first active fin in the second direction is greater than a length of the second active fin in the second direction.