A semiconductor device (100) includes: a first line (8) having a first end portion (8T); a second line (2) being insulated from the first line and having a second end portion (2T); a first electrically-conductive portion (9) provided in the neighborhood of the first and second end portions so as to be spaced apart therefrom; a dielectric layer (20) covering them; and a second electrically-conductive portion (38) on the dielectric layer. The dielectric layer (20) has a first contact hole (CH1) overlapping the first end portion and a second contact hole (CH2) overlapping the first electrically-conductive portion; the second electrically-conductive portion (38) is connected with the first end portion (8T) and the first electrically-conductive portion (9) within the first contact hole (CH1) and the second contact hole (CH2); the second end portion (2T) is insulated from the first electrically-conductive portion (9); the first electrically-conductive portion (9) includes a proximate portion (9T) protruding toward the first end portion; and the dielectric layer (20) has a first hole (H1) overlapping the proximate portion (9T) of the first electrically-conductive portion.

The present invention relates to a display panel including a static electricity preventing pattern and a display device having the same. An aspect of the present invention provides a display device or a display panel in which a dummy pattern having a pattern identical to or similar to a line of a signal area is positioned between the signal area and a non-signal area, in a pad including the signal area and the non-signal area.

A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part.

An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

A display panel includes: an electrostatic discharge (ESD) protection circuit area in a peripheral area surrounding a display area including pixels, the ESD protection circuit area including ESD protection circuits; a fan-out area in the peripheral area, including fan-out lines to receive data signals and a first pad to receive a first global signal; a common line area between the ESD protection circuit area and the fan-out area, including a first common line extending lengthwise in a pixel row direction; a first transmission line connecting lengthwise from the first pad to the first common line to transmit the first global signal to the first common line; and first global signal lines extending lengthwise in a pixel column direction from the first common line to the display area to concurrently transmit the first global signal to the pixels. The first transmission line is wider than the first global signal lines.

An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.

A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

A display device includes a flexible substrate, a buffer layer on the flexible substrate and including an inorganic material, a display area including a plurality of pixels on the buffer layer and each including a pixel circuit including a first thin film transistor (TFT), a second TFT, and a storage capacitor and a display device connected to the pixel circuit, and a non-display area that is adjacent to the display area. The flexible substrate includes at least one base layer, at least one inorganic barrier layer, and a shielding layer including a portion having a certain area and an opening adjacent to the portion.