A semiconductor structure is provided having improved electrostatic contact close to the dielectric pillar that separates a first device region from a second device region. The semiconductor structure includes a dielectric pillar located between a first vertical nanosheet stack of suspended semiconductor channel material nanosheets and a second vertical nanosheet stack of suspended semiconductor channel material nanosheets. Horizontal dielectric bridge structures can be located in the first and second device regions. The horizontal bridge structures connect each of the suspended semiconductor channel material nanosheets to a respective sidewall of the dielectric pillar. A dielectric spacer structure can laterally surround a lower portion of the dielectric pillar and be present in a semiconductor substrate. In some embodiments, the horizontal dielectric bridge structures can be omitted.

Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.

An array substrate has a display area and includes at least one pixel group, at least one pixel circuit group and at least one shift register circuit. The at least one pixel group is disposed in the display area. Each pixel group includes a plurality of pixels arranged in an array. Each pixel circuit group is disposed between two adjacent rows of pixels or two adjacent columns of pixels in a corresponding pixel group. Each pixel circuit group includes at least one pixel driving sub-circuit group. A shift register circuit is disposed between two rows of pixels or two columns of pixels that are different from two rows of pixels or two columns of pixels between which a pixel driving sub-circuit group is disposed.

A semiconductor device includes a semiconductor substrate, an internal circuit provided on the semiconductor substrate, a first and a second pads connected to the internal circuit, a first ESD protection circuit connectable to the first pad, and a second ESD protection circuit connectable to the second pad. The first ESD protection circuit includes a first ESD protection element, and the second ESD protection circuit includes a second and a third ESD protection elements. The second pad is connected to the internal circuit via the second ESD protection element, and the first pad is directly connected to the internal circuit.

A semiconductor device includes a first well region in a substrate and doped with impurities of a first conductivity type, a second well region in the substrate and doped with impurities of a second conductivity type, where the second well region is on internal sides of the first well region in a first direction that is parallel to an upper surface of the substrate, a first impurity region in the first well region and doped with impurities of the first conductivity type, a plurality of active regions in the second well region along the first direction and doped with impurities of the first conductivity type, a gate structure between the plurality of active regions in the first direction, a first dummy gate structure on the first impurity region and at least partially surrounding the second well region, and a plurality of wiring patterns.

An electro-static discharge (ESD) protection circuit includes a driver stack electrically connected between a first node that has a first reference voltage and a second node that has a second reference voltage. The ESD protection circuit further includes an input/output (I/O) pad electrically connected to the driver stack, wherein the driver stack is electrically between the I/O pad and each of the first node and the second node. The ESD protection circuit further includes a first ESD device electrically connected between the I/O pad and a third node that has a third reference voltage, wherein the I/O pad is electrically connected between the first ESD device and the driver stack.

A display device includes a substrate including a display area and a non-display area adjacent to the display area, a plurality of pixels being located in the display area, a driver located in the non-display area, a data line electrically connected to the driver to transmit a data signal to each of the plurality of pixels, a first driving voltage line and a second driving voltage line in the non-display area, and an antistatic portion in the non-display area and connected between the data line and the first driving voltage line. The display area further includes at least one first area electrically connected to one side of the driver and at least one second area electrically connected to another side of the driver. In addition, the non-display area includes a first non-display area corresponding to the first area and a second non-display area corresponding to the second area.

An anti-corrosion circuit, an array substrate and an electronic device are provided. The array substrate includes: source signal lines, provided in the display area, extending along a first direction and arranged sequentially along a second direction; a first power bus line, provided in the peripheral area and including a main body portion extending along the second direction; an electrostatic discharge protection circuit, provided on a side of the main body portion away from the display area and electrically connected to the source signal lines, and including first sub-signal lines and second sub-signal lines. The first sub-signal lines and the second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion is adjacent to one first sub-signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub-signal line.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

The present disclosure provides a semiconductor device. The semiconductor device includes a stack disposed in a first region of the semiconductor device, a plurality of channel members disposed in a second region of the semiconductor device and vertically stacked, and a metal gate wrapping around at least one of the channel members. The stack has first type epitaxial layers and second type epitaxial layers alternatingly arranged in a vertical direction. The first type epitaxial layers have a first material composition and the second type epitaxial layers have a second material composition different from the first material composition. The stack has a first implant region of a first conductivity type and a second implant region of a second conductivity type opposite the first conductivity type. The channel members have the first material composition.