A power semiconductor device according to example embodiments of the present disclosure may include: a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a drain region of the first conductivity type spaced apart inwardly from an edge of the well region by a first length and disposed in the well region; a JFET region of the first conductivity type on the drift layer outside of the well region; a gate electrode extending along an upper surface of the well region and having a ring shape, the gate electrode being disposed on the upper surface of the well region; a source electrode connected to the JFET region; and a drain electrode connected to the drain region.

A power semiconductor device according to example embodiments of the present disclosure may include: a substrate including SiC of a first conductivity type; a drift layer of the first conductivity type on the substrate; a well region of a second conductivity type on the drift layer; a drain region of the first conductivity type spaced apart inwardly from an edge of the well region by a first length and disposed in the well region; a JFET region of the first conductivity type on the drift layer outside of the well region; a gate electrode extending along an upper surface of the well region and having a ring shape, the gate electrode being disposed on the upper surface of the well region; a source electrode connected to the JFET region; and a drain electrode connected to the drain region.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A junction field-effect transistor device includes an integrated temperature sensor, and a method of making the same is disclosed. A temperature sensor material having a first charge carrier polarity is implanted into an area of semiconductor material having a second charge carrier polarity, with the area being located adjacent to the junction field-effect transistor. The sensor material contains dopants and exhibits an electrical resistance that increases with a number of ionized ones of the dopants. The number of ionized dopants increases with the temperature of the material. First and second electrical terminals are provided spaced-apart on the sensor material for measuring the electrical resistance of the material. The measured electrical resistance may be translated into a temperature value for the junction field-effect transistor.

A semiconductor device includes a substrate of a first conductivity type, a drift layer of the first conductivity type on the substrate, a well region of a second conductivity type on the drift layer, a source region of the first conductivity type on the well region, a gate trench extending through the source region and the well region, and extending into the drift layer, a gate insulating layer in the gate trench, a gate electrode on the gate insulating layer, a shield region of the second conductivity type below the gate insulating layer and in a section of the gate trench that extends into the drift layer, and a cap region of the first conductivity type on a side of the shield region and in the section of the gate trench that extends into the drift layer.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (IO) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the IO-circuits; the second level is disposed over the first level.

Embodiments of the present disclosure illustrate a semiconductor device. The semiconductor device comprises a silicon carbide epitaxial layer, comprising: a p-type well region; a junction field effect region adjacent to the p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The semiconductor device further comprises an island-shaped oxide layer on the junction field effect region; a gate oxide layer covering the p-type well region, the junction field effect region, the heavily doped n-type region, the heavily doped p-type region and the island-shaped oxide; and a polycrystalline silicon layer on the gate oxide layer without contacting the island-shaped oxide.

A method includes providing a two-level gallium nitride (GaN) epitaxial substrate comprising a first GaN drift layer characterized by a first doping concentration and a second GaN drift layer disposed on the first GaN drift layer and characterized by a second doping concentration higher than the first doping concentration and forming a plurality of pedestals in the second GaN drift layer. Each of the plurality of pedestals is laterally separated by one of a plurality of funnels. The method also includes performing a channel regrowth process to regrow a plurality of n-type GaN channels, each disposed in one of the plurality of funnels, and performing a gate regrowth process to regrow p-type GaN. The method further includes patterning the p-type GaN to form a plurality of p-type GaN gates disposed in one of the plurality of n-type GaN channels, and forming source contacts, gate contacts, and a drain contact.