A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is deposited over the substrate and over a lower portion of the fin. A glass of a second dopant type is deposited over the substrate and the fin. The glass is annealed to drive the dopants into the fin and the substrate. The glass is removed and a first and a second contact are formed over the fin without contacting the lower portion of the fin.

Provided are a silicon carbide semiconductor device that is capable of preventing breakdown voltage degradation in the edge termination structure and a method of manufacturing the same.

The p-type regions 31, 32 and the p-type region 33, which serves as an electric field relaxation region and is connected to the first p-type base regions 10, are positioned under the step-like portion 40, and the bottom surfaces of the p-type regions 31, 32, 33 are substantially flatly connected to the bottom surface of the first p-type base regions 10.

The first base regions have an impurity concentration of 410.sup.17 cm.sup.3 or higher. The p-type region 33 is designed to have a lower impurity concentration than the first base regions 10 and higher than the p-type regions 31, 32. In this way, the breakdown voltage degradation in the edge termination structure 102 can be prevented.

A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.

A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.

One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality of doped regions in the same P-type semiconductor substrate and separated by a punch through stop region. An N-type region is formed under the one or more Zener diodes.

Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.

Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.

A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

A semiconductor device includes: an n.sup.+-type drain region deposited at an upper part of a p-type semiconductor base body; an n-type drift region deposited to be in contact with the n.sup.+-type drain region; an n.sup.+-type source region opposed to the n.sup.+-type drain region with the n-type drift region interposed; a p-type gate region deposited to be in contact with the n-type drift region; an interlayer insulating film covering the n-type drift region; a resistive element having a spiral-like planar shape provided inside the interlayer insulating film; a drain electrode wire connected to the n.sup.+-type drain region and one end of the resistive element; a source electrode wire connected to the n.sup.+-type source region; a gate electrode wire connected to the p-type gate region; and a potential-dividing terminal wire connected to the resistive element, wherein a gap between the source electrode wire and an outermost circumference of the resistive element is constant.