Disclosed are a vertical trench coupling capacitance gate-controlled junction field effect transistor and a manufacturing method thereof. The vertical trench coupling capacitance gate-controlled junction field effect transistor includes a substrate of a first doping type, an epitaxial layer of the first doping type, and a plurality of repeating units disposed adjacently; where the epitaxial layer is disposed on the substrate, the substrate is served as a drain region, and each of the repeating units includes: two source regions of the first doping type; a trench; a gate of the second doping type; a dielectric; and a coupling capacitance upper electrode, where the gate is indirectly controlled by the coupling capacitance upper electrode spaced with the dielectric layer.

A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

A chip includes a first capacitor. The first capacitor includes first electrodes formed from metal layer M0, wherein the first electrodes are coupled to one another. The first capacitor also includes second electrodes formed from the metal layer M0, wherein the second electrodes are coupled to one another.

A method can include receiving a first power supply voltage at a first terminal at a first side of an IC device and providing a row of stacked pairs of insulated gate field effect transistor (IGFETs) substantially at the second side of the IC device. Each stacked pair can include a first and second IGFET of different conductivity types. Each IGFET can include multiple channels and a control gate that substantially surrounds the channels. A first power supply can be coupled from the first power supply terminal to a first source of one IGFET of the stacked pair via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side below the row of stacked pairs. Corresponding devices and systems are also disclosed.

A semiconductor device includes: a first conductor layer; a second conductor layer; an oxide semiconductor layer provided between the first conductor layer and the second conductor layer; a gate electrode provided next to the oxide semiconductor layer; and a gate insulating film provided between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes at least one of indium, gallium, zinc, aluminum, tin, titanium, silicon, germanium, copper, arsenic, and tungsten and oxygen and includes a first end and a second end. The first conductor layer includes indium, tin, oxygen, and a first element that is at least one of nitrogen, sulfur, selenium, tellurium, hafnium, tantalum, tungsten, rhenium, osmium, iridium, bismuth, lanthanum, yttrium, zinc, cadmium, and mercury. The first end of the oxide semiconductor layer is in contact with the first conductor layer.

Semiconductor devices and fabricating methods thereof are provided. A semiconductor device including vertical transistors and storage units coupled with the vertical transistors correspondingly is provided. The vertical transistor includes a semiconductor layer and a gate structure. The semiconductor layer includes a vertical portion extending in a vertical direction and a first lateral portion extending from a first end of the vertical portion in a lateral direction. The gate structure is coupled to the vertical portion of the semiconductor layer and extends in the vertical direction. The first lateral portions of the semiconductor layers of two adjacent vertical transistors in the lateral direction are connected with each other.

A high electron mobility transistor may include a channel layer, a barrier layer positioned on the channel layer, a gate electrode positioned on the barrier layer, a source electrode and a drain electrode connected to the channel layer and positioned at both sides of the gate electrode, a first electrode positioned on the gate electrode, a second electrode overlapping the first electrode, and an insulating layer positioned between the first electrode and the second electrode. The first electrode and the second electrode may be electrically insulated from each other. The first electrode may be connected to the source electrode and a first power voltage. The second electrode may be connected to a second power voltage higher than the first power voltage.

First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.