A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

In a semiconductor device, a first active region has a first -shape, and the second active region has a second -shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.

A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.

According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.

The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Fabrication of a field-effect transistor is performed on a substrate comprising a film made from first semiconductor material, a gate dielectric covered by a gate electrode, source and drain areas separated by the gate electrode, a protection layer covering gate electrode and source and drain areas, and an access hole to the source area and/or to drain area. Metallic material is deposited in the access hole in contact with the first semiconductor material of the source and/or drain area. An electrically conducting barrier layer that is non-reactive with the first semiconductor material and with the metallic material is deposited before reaction of metallic material with first semiconductor material. Transformation heat treatment of the metallic material with the semiconductor material is performed to form a metallic material having a base formed by the semiconductor material generating a set of stresses on a conduction channel arranged between the source and drain areas.

A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.