A power semiconductor device includes a first contact, a second contact, and a semiconductor volume disposed between the first contact and the second contact. The semiconductor volume includes an n-doped field stop layer configured to spatially delimit an electric field that in the semiconductor volume during operation of the power semiconductor device, a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode. The tunnel diode is located in the vicinity of, or adjacent to, or within the field stop layer. The tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes. Further, a method for producing such devices is provided.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a top surface. The semiconductor device structure includes a first pillar structure over the substrate. The first pillar structure includes a first heavily n-doped layer, a first p-doped layer, an n-doped layer, and a first heavily p-doped layer, which are sequentially stacked together. The first pillar structure extends in a direction away from the substrate.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

A semiconductor device includes an electrostatic discharge (ESD) device formed adjacent to a first fin field effect transistor (finFET). The device includes a substrate, the first finFET and the ESD device. The first finFET is formed such that it includes finFET fins extending from the substrate. The ESD device includes two vertically stacked PN diodes including vertically stacked first, second, third and fourth layers. The first layer is an N doped layer and is disposed directly over the substrate, the second layer is a P doped layer and is disposed directly over the first layer, the third layer is an N doped layer and is disposed directly over the second layer and the fourth layer is a P doped layer and is disposed directly over the third layer.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a hybrid memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency.

The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.

A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.