A circuit can include a transistor, a capacitive element, and a rectifying element. The rectifying element and the capacitive element can be serially connected and coupled to the current-carrying terminals of the transistor. An electronic device may include part of the circuit. The electronic device can include a diode that includes a horizontally-oriented semiconductor member and a vertically-oriented semiconductor member having different conductivity types. The ends of the horizontally-oriented semiconductor and vertically-oriented semiconductor members physically contact each other. A process of forming an electronic device can include forming a semiconductor layer and forming a second semiconductor member. In a finished device, a diode includes a junction between dopants of first and second conductivity types within the semiconductor layer, within the semiconductor member, or at an interface between the semiconductor layer and the semiconductor member.

An IGBT includes a floating P well, and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a waved contour so that it has thinner portions and thicker portions. When the device is on, electrons flow laterally from an N+ emitter, and through a first channel region. Some electrons pass downward, but others pass laterally through the floating N+ well to a local bipolar transistor located at a thinner portion of the floating P type well. The transistor injects electrons down into the N drift layer. Other electrons pass farther through the floating N+ well, through the second channel region, and to an electron injector portion of the N drift layer. The extra electron injection afforded by the floating well structures reduces V.sub.CE(SAT). The waved contour is made without adding any masking step to the IGBT manufacturing process.

A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450 C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.

A semiconductor device including: a semiconductor substrate; a temperature sensing unit provided on a front surface of the semiconductor substrate; an anode pad and a cathode pad electrically connected with the temperature sensing unit; a front surface electrode being set to a predetermined reference potential; and a bidirectional diode unit electrically connected in a serial bidirectional way between the cathode pad and the front surface electrode is provided. The bidirectional diode unit may be arranged between the anode pad and the cathode pad on the front surface.

Provided is a semiconductor device that includes a drift region that is of a first conductivity type and is provided in a semiconductor substrate; a base region that is of a second conductivity type and is provided above the drift region; an accumulation region that is of the first conductivity type provided between the base region and the drift region; and an electric field relaxation region that is provided between the base region and the accumulation region, wherein the boundary between the electric field relaxation region and the accumulation region is a location for a half-value for the peak of the doping concentration of the accumulation region, and an integrated concentration of the electric field relaxation region is greater than or equal to 5E14 cm.sup.2 and less than or equal to 5E15 cm.sup.2.

A semiconductor device includes a drift region extending from a first surface into a semiconductor portion. A body region between two portions of the drift region forms a first pn junction with the drift region. A source region forms a second pn junction with the body region. The pn junctions include sections perpendicular to the first surface. Gate structures extend into the body regions and include a gate electrode. Field plate structures extend into the drift region and include a field electrode separated from the gate electrode. A gate shielding structure is configured to reduce a capacitive coupling between the gate structures and a backplate electrode directly adjoining a second surface.

A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.

A semiconductor device includes a drift layer of a first conductivity-type, having a superjunction structure, including a plurality of columns of a second conductivity-type, a plane pattern of each of the columns extends along a parallel direction to the principal surface of the layer, the columns are arranged at regular intervals; a plurality of well regions of the second conductivity-type provided in a surface-side layer of the layer of the first conductivity-type; a plurality of source regions of the first conductivity-type selectively provided in the plurality of well regions; a gate insulating film provided on the principal surface; an array of gate electrodes disposed on the gate insulating film, each of the gate electrodes is provided so as to bridge the corresponding source regions in a pair of neighboring two well regions; and a temperature detection diode provided at a partial area defined in the array of the gate electrodes.

A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.

A method for forming a semiconductor device includes forming an electrical structure at a main surface of a semiconductor substrate and carrying out an anodic oxidation of a back side surface region of a back side surface of the semiconductor substrate to form an oxide layer at the back side surface of the semiconductor substrate.