A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.

A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between it and electric field relaxation p-layer 16, low resistance n-layer 17 is provided. Low resistance n-layer 17 is formed deeper than trench T, and shallower than electric field relaxation p-layer 16, being connected to n.sup.-layer (drift layer) 12 just thereunder, and thus low resistance n-layer 17 and n.sup.-layer 12 are integrated to form a drift layer. Although low resistance n-layer 17 is n-type as is n.sup.-layer 12, donor concentration thereof is set higher than that of n.sup.-layer 12, thereby low resistance n-layer 17 having a resistivity lower than that of n.sup.-layer 12. This low resistance n-layer 17 is provided in on-current path (between electric field relaxation p-layer 16 and trench T), whereby low resistance n-layer 17 can lower the resistance to on-current.

Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon layer is recessed in a first region of the substrate structure and remains unrecessed in a second region of the substrate structure. A protective layer having a first germanium concentration is formed above the recessed silicon layer in the first region, which extends along a sidewall of the unrecessed silicon layer of the second region. A semiconductor layer having a second germanium concentration is disposed above the protective layer in the first region of the substrate structure, where the first germanium concentration of the protective layer inhibits lateral diffusion of the second germanium concentration from the semiconductor layer in the first region into the unrecessed silicon layer in the second region of the substrate structure.

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided.

A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

The present inventive concept relates to a thin film manufacturing method and a thin film. The thin film manufacturing method comprises: an adsorption step of adsorbing a high-k material on a substrate by spraying a source gas consisting of a high-k material; a deposition step of depositing a thin film consisting of the high-k material on the substrate by spraying a reaction gas that reacts with the source gas; and a crystallization step of crystallizing the high-k material using plasma.

A substrate processing device. The device comprises: a first source supply unit; a second source supply unit; a first supply line for connecting the first source supply unit to a spraying unit; a second supply line for connecting the second source supply unit to the spraying unit; a mixing unit provided at the first supply line to be arranged between the first source supply unit and the spraying unit; a first connection line for connecting the second supply line to the first supply line and/or the mixing unit; and a first path change unit provided at a first connection point at which the first connection line is connected to the second supply line, wherein the first path change unit changes the flow path of a second source gas supplied from the second source supply unit.