A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

The present disclosure provides a TFT, an array substrate, their manufacturing method, and a display device. The method for manufacturing the TFT includes a step of forming a pattern of a semiconductor active layer on a transparent substrate through a patterning process, and the pattern of the semiconductor active layer includes a lanthanum boride pattern.

A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

The described embodiments may provide a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be coupled to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be coupled to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants.

Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

A method for forming a high electron mobility transistor (HEMT) device with a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN), and an HEMT device formed by the method is disclosed. In one embodiment, the method includes forming a channel layer stack on a substrate, the channel layer stack having a plurality of alternating layers of one or more undoped gallium nitride (GaN) layers and one or more carbon doped gallium nitride layers (c-GaN). The method further includes forming a barrier layer on the channel layer stack. In one embodiment, the channel layer stack is formed by growing each of the one or more undoped gallium nitride (GaN) layers in growth conditions that suppress the incorporation of carbon in gallium nitride, and growing each of the one or more carbon doped gallium nitride (c-GaN) layers in growth conditions that promote the incorporation of carbon in gallium nitride.

Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

The present disclosure discloses a vertical stack-type memory device may including a word line extending in a horizontal direction and having a vertical through-hole region, a vertical bit line arranged vertically to pass through the through-hole region, a channel layer pattern arranged to surround the vertical bit line inside the through-hole region, a body insulating layer disposed between the vertical bit line and a remaining portion except for the one end of the channel layer pattern, an electrode member arranged to surround an outer peripheral surface of the channel layer pattern at a height higher than the word line, a dielectric layer pattern disposed between the word line and the channel layer pattern and having a structure surrounding the electrode member, and a plate electrode in contact with the dielectric layer pattern above the word line.

The present disclosure discloses a manufacturing method including forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer; forming a patterned stack including at least one pattern portion having a first sacrificial layer obtained from the first sacrificial layer by patterning the stack; forming a structure including the patterned stack and the insulating material by filling empty spaces on both sides of the at least one pattern portion with an insulating material; forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure; forming a horizontal hole by removing the first sacrificial layer pattern exposed by the first vertical hole; and forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole.