The present disclosure provides a hybrid heterojunction solar cell, a cell component, and a preparation method, the hybrid heterojunction solar cell comprises a semiconductor substrate having a substrate front surface and a substrate back surface opposite to each other, wherein the substrate front surface is close to a light-facing side of the cell and the substrate back surface is close to a backlight side of the cell; at least two composite layers located on one side of the substrate front surface, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface. The hybrid heterojunction solar cell, cell component and a preparation method provided by this disclosure can achieve a stable passivation effect on the cell surface, reduce light absorption in the non-metallic areas of the cell, and achieve better process control at the same time.

A solar cell, comprising a silicon cell main body (110), a first transparent conductive oxide layer (120), a second transparent conductive oxide layer (130), an insulating passivation layer (160), and a second electrode (150), wherein the insulating passivation layer (160) covers edges of the back face of the silicon cell main body (110), and at the edges of the back face of the silicon cell main body (110), the second transparent conductive oxide layer (130) and the first transparent conductive oxide layer (120) are arranged spaced apart from each other by means of the insulating passivation layer (160) arranged therebetween.

A solar cell, comprising a silicon cell main body (110), a first transparent conductive oxide layer (120), a second transparent conductive oxide layer (130), an insulating passivation layer (160), and a second electrode (150), wherein the insulating passivation layer (160) covers edges of the back face of the silicon cell main body (110), and at the edges of the back face of the silicon cell main body (110), the second transparent conductive oxide layer (130) and the first transparent conductive oxide layer (120) are arranged spaced apart from each other by means of the insulating passivation layer (160) arranged therebetween.

The present disclosure provides a solar cell, a photovoltaic module, and a method for packaging a solar cell. An example method of packaging a solar cell includes arranging a protective layer on a light-receiving surface of the solar cell. A light transmittance of the protective layer is greater than a light transmittance threshold, and a heat-resistant temperature of the protective layer is greater than or equal to a heat-resistant temperature threshold.

The present disclosure provides a solar cell, a photovoltaic module, and a method for packaging a solar cell. An example method of packaging a solar cell includes arranging a protective layer on a light-receiving surface of the solar cell. A light transmittance of the protective layer is greater than a light transmittance threshold, and a heat-resistant temperature of the protective layer is greater than or equal to a heat-resistant temperature threshold.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

A portable solar photovoltaic (PV) electricity generator module comprises a plurality of smart power slat (SPS) units, each SPS unit comprising a plurality of solar cells electrically connected together based on a specified cell interconnection design, and, at least one power maximizing integrated circuit collecting electricity generated by the plurality of solar cells. The plurality of SPS units are mechanically connected such that the SPS units can be retracted for volume compaction of the module, and can be expanded for increasing PV electricity generation by the module. The module can be used as part of an electric power supply with a maximum power point tracking (MPPT) power optimizer, storage battery and leads to connect to a load. The load can be AC or DC.

A portable solar photovoltaic (PV) electricity generator module comprises a plurality of smart power slat (SPS) units, each SPS unit comprising a plurality of solar cells electrically connected together based on a specified cell interconnection design, and, at least one power maximizing integrated circuit collecting electricity generated by the plurality of solar cells. The plurality of SPS units are mechanically connected such that the SPS units can be retracted for volume compaction of the module, and can be expanded for increasing PV electricity generation by the module. The module can be used as part of an electric power supply with a maximum power point tracking (MPPT) power optimizer, storage battery and leads to connect to a load. The load can be AC or DC.

A method of manufacturing a carrier-selective contact junction silicon solar cell includes: preparing a conductive silicon substrate; forming a first passivation layer and a second passivation layer on and under the conductive silicon substrate, respectively; forming an electron-selective contact layer under the second passivation layer; forming a hole-selective contact layer on the first passivation layer; forming an upper transparent electrode on the hole-selective contact layer; forming an upper metal electrode on the upper transparent electrode; and forming a lower metal electrode under the electron-selective contact layer. In forming the hole-selective contact layer, a sandwich-structured multilayer film is formed by depositing a copper iodide thin film on a top surface and a bottom surface of an iodine thin film, and a single-film copper iodide thin film is formed by low-temperature annealing the sandwich-structured multilayer film.