A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

A process can be implemented to form adjacent transistors separated by a shallow trench isolation (STI), where the STI is formed after forming gates and sources/drains of the transistors. The STI can be formed by an active area cut using a mask to form a rectangular opening for filling with a STI dielectric. Using an active area mask providing a rectangular-like shape after forming gate stacks and source/drains, a memory device can be constructed having transistors separated by a STI having a recess from active areas of the transistors by at most 50 nm.

The semiconductor device includes a semiconductor layer having an active portion and a gate finger portion, an MIS transistor formed at the active portion including a gate trench and a source region, a channel region and a drain region sequentially along a side surface of the gate trench, a plurality of first gate finger trenches arranged by an extended portion of the gate trench, a gate electrode embedded each in the gate trench and the first gate finger trench, a second conductive-type first bottom-portion impurity region formed at least at a bottom portion of the first gate finger trench, a gate finger which crosses the plurality of first gate finger trenches and is electrically connected to the gate electrode, and a second conductive-type electric field relaxation region formed more deeply than the bottom portion of the first gate finger trench between the mutually adjacent first gate finger trenches.

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

Semiconductor devices that include a replacement metallic gate electrode and a gate-level semiconductor structure can be formed on a seme semiconductor substrate by providing an etch-stop structure that prevents replacement of the gate-level semiconductor structure, and by replacing a sacrificial semiconductor gate electrode with the replacement metallic gate electrode. The gate-level semiconductor structure may include a semiconductor gate electrode of a field effect transistor, or a semiconductor material strip that can be employed as a resistor. In one embodiment, the etch-stop structure and an overlying sacrificial structure may be replaced with another replacement metallic gate electrode. In another embodiment, a silicide region may be formed on the semiconductor gate electrode.

Semiconductor devices that include a replacement metallic gate electrode and a gate-level semiconductor structure can be formed on a seme semiconductor substrate by providing an etch-stop structure that prevents replacement of the gate-level semiconductor structure, and by replacing a sacrificial semiconductor gate electrode with the replacement metallic gate electrode. The gate-level semiconductor structure may include a semiconductor gate electrode of a field effect transistor, or a semiconductor material strip that can be employed as a resistor. In one embodiment, the etch-stop structure and an overlying sacrificial structure may be replaced with another replacement metallic gate electrode. In another embodiment, a silicide region may be formed on the semiconductor gate electrode.

Semiconductor devices that include a replacement metallic gate electrode and a gate-level semiconductor structure can be formed on a seme semiconductor substrate by providing an etch-stop structure that prevents replacement of the gate-level semiconductor structure, and by replacing a sacrificial semiconductor gate electrode with the replacement metallic gate electrode. The gate-level semiconductor structure may include a semiconductor gate electrode of a field effect transistor, or a semiconductor material strip that can be employed as a resistor. In one embodiment, the etch-stop structure and an overlying sacrificial structure may be replaced with another replacement metallic gate electrode. In another embodiment, a silicide region may be formed on the semiconductor gate electrode.

A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.

A semiconductor device includes a substrate including a source region and a drain region; a word line structure including a word line dielectric layer in the substrate, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line penetrating through the top and bottom capping layers and extending into the source region; and a cell contact penetrating through the top and bottom capping layers and extending into the drain region.