A semiconductor device includes a first interconnection line extending in a first direction; a second interconnection line extending in a second direction; and a memory cell disposed between the first interconnection line and the second interconnection line. The memory cell includes a first electrode; a first memory layer including a ferroelectric layer over the first electrode; a second electrode over the first memory layer; a second memory layer including a high-k dielectric layer over the second electrode; an oxygen reservoir layer over the second memory layer; and a third electrode over the oxygen reservoir layer.

The present disclosure relates to a trench-type DMOS device and manufacturing method therefor. The trench-type DMOS device includes an expansion gate layer disposed on an inner surface of a gate insulation layer, and the expansion gate layer includes a first expansion gate region with a second conduction type, a second expansion gate region with a first conduction type, and a third expansion gate region, which improves a contradiction relationship between voltage resistance and specific on-resistance of the trench-type DMOS device. Therefore, the trench-type DMOS device has both high voltage resistance and low specific on-resistance. The trench-type DMOS device has a longitudinal voltage resistance structure, which reduces device area and further decreases device on-resistance. At the same time, a source region and a drain region in the trench-type DMOS device may be led out on its front surface, which is compatible with CMOS.