An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

A semiconductor memory device includes first and second stacked films, each of which includes a plurality of conductive layers and a plurality of insulating layers alternately stacked one on top of another, a first core insulating film penetrating the stacked film and containing an oxide, a channel semiconductor film around the first core insulating film and penetrating the first stacked film, a tunnel insulating film around the channel semiconductor film and penetrating the first stacked film, and a charge storage film around the tunnel insulating film and penetrating the first stacked film. The first stacked film additionally includes a second core insulating film around the first core insulating film, penetrating the first stacked film and containing a nitride, and a third core insulating film between the channel semiconductor film and the second core insulating film, penetrating the first stacked film, and including an oxide.

Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.