Patent classifications
H10D30/687
MULTIPLE THRESHOLD STACKED FIELD EFFECT TRANSISTORS
Embodiments are disclosed for a semiconductor structure that includes a first stacked field effect transistor (FET) configured as a shared gate device, and a second stacked FET configured to operate as two independent gate devices. The first stacked FET includes a first top FET having a first top work-function metal (WFM) and a first bottom FET having a first bottom WFM. Further, the first top WFM and the first bottom WFM are connected through shared gate connectors disposed on either side of a middle dielectric isolation (MDI) layer. Further, the second stacked FET includes a second top FET having a second top WFM and a second bottom FET having a second bottom WFM. Further, the second top WFM and the second bottom WFM are separated by the MDI layer and a pair of spacer shoulders disposed on either side of the MDI layer.