A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material.

A semiconductor device includes an n-type buried layer, a first N-well region, a p-type body region, a first source/drain region, a second source/drain region, a gate structure, a second N-well region, and a first silicide region. The n-type buried layer in a substrate. The first N-well region is over the n-type buried layer. The p-type body region abuts the first N-well region. The first source/drain region is in the first N-well region. The second source/drain region is in the p-type body region. The gate structure extends across a boundary of the first N-well region and the p-type body region. The second N-well region is over the n-type buried layer. The first silicide region forms a Schottky contact with the second N-well region.