A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

There is provided a structure of a nano memory system. The disclosed unit nano memory cell comprises a single isolated nanoparticle placed on the surface of a semiconductor substrate (301) and an adjacent nano-Schottky contact (303). The nanoparticle works as a storage site where the nano-Schottky contact (303) works as a source or a drain of electrons, in or out of the semiconductor substrate (301), at a relatively small voltage. The electric current through the nano-Schottky contact (303) can be turned on (reading 1) or off (reading 0) by charging or discharging the nanoparticle. Since the electric contact is made by a nano-Scottky contact (303) on the surface and the back contact of the substrate (301), and the charge is stored in a very small nanoparticle, this allows to attain the ultimate device down-scaling. This would also significantly increase the number of nano memory cells on a chip. Moreover, the charging and discharging (writing/erasing), as well as the reading voltages are lower than those needed for CMOS based flash memory cells, due to the small nano-Schottky contact (301) and the small size of the nanoparticle for charge storage.

A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

An integrated structure according to a preferred embodiment may include a silicon or silicon-on-insulator (SOI) substrate, a conductive layer spaced apart from the substrate and including a metal or a metal compound, and a diffusion barrier layer provided therebetween. The substrate and the diffusion barrier layer may directly contact and form a van der Waals junction. Since the diffusion barrier layer may block diffusion of metal atoms into the substrate lattice by blocking movement of materials (atoms) between the substrate and the conductive layer and may also control injection of holes from the conductive layer toward the substrate, defects at the metal-semiconductor interface may be controlled to overcome the limitations of ultra-fine and highly integrated semiconductors.

A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region.

A semiconductor device includes, on a semiconductor substrate of a first conductivity type, an active region through which a main current flows, a terminal region surrounding a periphery of the active region, and an intermediate region between the active region and the terminal region. The semiconductor device has, in the active region, a front electrode disposed on a first main surface of the semiconductor substrate and connected to a first semiconductor region of a second conductivity type. In the intermediate region, the semiconductor device has a source ring electrically connected to the front electrode and to a second semiconductor region of the second conductivity type for extracting hole current. A contact between the front electrode in the active region and the first semiconductor region is an ohmic contact. A contact between the source ring in the intermediate region and the second semiconductor region includes a Schottky junction or a heterojunction.

Provided is a semiconductor device. The semiconductor device includes a semiconductor layer including silicon, a first silicide layer in the semiconductor layer, and a second silicide layer provided on the first silicide layer. The first silicide layer includes a metal other than titanium, and the second silicide layer includes TiSi.sub.2 having a C54 crystallization structure. A contact resistance of the semiconductor device may be reduced.

A p-GaN gate tunnel junction HEMT includes a nucleation layer, buffer layer, nitride-based channel layer, nitride-based barrier layer, p-type GaN layer, gate electrode, source electrode, drain electrode, and surface passivation layer. The nucleation and buffer layers are disposed on a substrate, with the nitride-based channel layer above. The nitride-based barrier layer is positioned on the nitride-based channel layer, creating a 2DEG channel between the channel and barrier layers. The p-type GaN layer is positioned on the nitride-based barrier layer. The gate electrode is positioned on the p-type GaN layer. The source electrode forms a tunnel junction with the 2DEG channel, and the drain electrode is placed on the nitride-based barrier layer. The passivation layer covers the nitride-based barrier layer with portions between the gate-source and gate-drain regions.