A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.

One embodiment of the present disclosure seeks to provide a thin film transistor and display device comprising: an active layer; a cover insulating film on the active layer; a first cover layer on the cover insulating film; and a gate electrode spaced apart from the active layer and at least partially overlapping the active layer, wherein the first cover layer covers an top surface of the cover insulating film and a side surface of the active layer, and the first cover layer includes an oxide semiconductor material and has a resistivity greater than that of the active layer.

Provided herein is a display device and a method of fabricating the display device. The display device includes a substrate including a display area and a non-display area, a via layer disposed in the display area, electrodes disposed on the via layer and spaced apart from each other, light emitting elements disposed between the electrodes, dummy pattern layers disposed in the non-display area, and dummy electrodes disposed on the dummy pattern layers. The via layer and the dummy pattern layers may be disposed on a same layer. The electrodes and the dummy electrodes may be disposed on a same layer.

A thin film transistor includes an active layer comprising: a first region; a second region on one side of the first region; and a third region on another side of the first region, wherein when a direction connecting source and drain electrodes is a first direction, the first, second, and third regions are along a second direction, and the first region comprises: a channel portion overlapping with the gate electrode; a first connecting portion on one side of the channel portion; And a second connecting portion on the other side of the channel portion, wherein the second region includes first and second dopant reduction portions, the third region includes third and fourth dopant reduction portions, and in a plane view, the gate electrode is inside the active layer, and the first, second, third, and fourth dopant reduction portions each have a higher resistivity than the first and second connecting portions.