A method includes forming a plurality of thermal sensing elements at predetermined locations on a semiconductor chip proximate to a target location, measuring a temperature of the semiconductor chip at each predetermined location using a corresponding one of the plurality of thermal sensing elements, and determining a temperature at the target location using the temperatures measured at each of the predetermined locations.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

An integrated circuit (IC) structure is described, including a substrate and a device on the substrate. The IC structure also includes a first contact field plate above the device. The IC structure further includes a dielectric layer between the first contact field plate and the device. The IC structure also includes a pressure/strain terminal coupled to the first contact field plate.

A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts. The first conductive part has a portion spaced apart from the first antenna part in the second direction with the exposed part therebetween as viewed in the thickness direction.

A MIS capacitor and a method of making the same. The capacitor includes a semiconductor substrate having a first part having a first conductivity type and contact regions for coupling the first part to an output node. The substrate has dielectric on a surface of the first part and electrodes on the dielectric. The substrate has a second part having a second conductivity type and a third part having the first conductivity type. The third part is coupleable to a supply voltage. The second part is located between the first part and the third part. The first part and the second part form a first p-n junction and the second part and the third part form a second p-n junction. A reference contact is provided for coupling the second part to a reference voltage. A further contact region is provided for coupling the second part to the output node.

A packaged integrated circuit device includes a die that includes integrated radio frequency (RF) circuitry. The packaged integrated circuit device also includes a package substrate including metal layers electrically connected to the RF circuitry. The packaged integrated circuit device further includes an impedance adapter electrically connected to the RF circuitry and disposed between the die and the package substrate. The impedance adapter includes a passive component disposed on or in a body of the impedance adapter.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is over the first side of the first substrate. The second substrate includes a semiconductor material, and a Schottky diode electrically coupled to the first conductive layer. The Schottky diode is configured by a first doped region in a first portion of the semiconductor material and a first contact structure. The first doped region contains a dopant at a concentration different from a remainder of the first portion of the semiconductor material to form a Schottky contact with the first contact structure.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.

A semiconductor device includes a buried semiconductor substrate layer interposed between a lower semiconductor substrate layer of a different conductivity type and an upper semiconductor substrate layer. A first isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a first insulating material formed at an inner sidewall of the first isolation trench, and is filled with a first electrically conductive material. A second isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a second insulating material formed at an inner sidewall and a bottom of the second isolation trench, and is either devoid of a second electrically conductive material or only a minor portion of the second isolation trench is filled with the second electrically conductive material.