H10D84/209

CHIP COMPONENT

A chip component includes a chip component main body, an electrode pad formed on a top surface of the main body, a protective film covering the top surface of the main body and having a contact hole exposing the pad, and an external connection electrode electrically connected to the pad via the hole and having a protruding portion, which, in a plan view looking from a direction perpendicular to a top surface of the pad, extends to a top surface of the film and protrudes further outward than a region of contact with the pad over the full periphery of an edge portion of the hole. A method for manufacturing the component includes forming the pad on the main body's top surface, forming the protective film, forming the hole in the film so as to expose the pad, and forming the electrode electrically connected to the pad via the hole.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
20170207295 · 2017-07-20 ·

A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.

Three precision resistors of different sheet resistance at same level

An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.

METHODS FOR PRODUCING POLYSILICON RESISTORS

A method for producing a polysilicon resistor device may include: forming a polysilicon layer; implanting first dopant atoms into at least a portion of the polysilicon layer, wherein the first dopant atoms include deep energy level donors; implanting second dopant atoms into said at least a portion of said polysilicon layer; and annealing said at least a portion of said polysilicon layer.

Polysilicon design for replacement gate technology

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

DIFFUSED RESISTOR

A diffused resistor and method for forming a diffused resistor are provided. The diffused resistor comprises a substrate having a first conductivity type; a first well within the substrate having a second conductivity type; and a second well within the first well having the first conductivity type. The resistor further comprises a first and second contact for coupling the resistor to further circuitry. The first and second contacts are each coupled to both the first well and the second well.

RESISTOR STRUCTURE WITH CAPPING STRUCTURE ON TFR LAYER
20250072013 · 2025-02-27 ·

Various embodiments of the present disclosure are directed towards an integrated chip including a thin film resistor (TFR) layer overlying a semiconductor substrate. A first conductive structure is disposed on an outer region of the TFR layer. The first conductive structure comprises a lateral portion adjacent to a vertical portion. A height of the vertical portion is greater than a height of the lateral portion. A capping structure is disposed on a middle region of the TFR layer and abuts the vertical portion of the first conductive structure.

FLEXIBLE AND STRETCHABLE SENSORS FORMED BY PATTERNED SPALLING
20170146474 · 2017-05-25 ·

A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.

Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
09660015 · 2017-05-23 · ·

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Chip component

A chip component includes a substrate, an element circuit network including a plurality of element parts formed on the substrate, an external connection electrode provided on a surface of the substrate to provide external connection for the element circuit network, a plurality of fuses formed on the substrate and disconnectably connecting each of the plurality of element parts to the external connection electrode, a solder layer formed on an external connection terminal of the external connection electrode and a resin film which covers the surface of the substrate and other surface which intersects the surface of the substrate.