A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.

A serpentine resistor within a back end of line (BEOL) level of a substrate includes a plurality of first sections oriented in a first horizontal direction, at least one second section oriented in a second horizontal direction, a plurality of vertical sections, and at least one lateral turn between the first horizontal direction and the second horizontal direction. The serpentine resistor may have a serpentine shape in the vertical plane and the horizontal plane, and may extend between two bonded substrates, providing higher resistance values compared to conventional BEOL resistors.

An integrated circuit includes active regions on an upper surface of a semiconductor substrate and having no electrical connection on the semiconductor substrate, an isolation layer on the upper surface of the semiconductor substrate and defining the active regions, and polysilicon resistors on the active regions and the isolation layer. The polysilicon resistors extend in a second direction that is perpendicular to a first direction in which the active regions extend, and are configured such that the number of active regions overlapping each of the polysilicon resistors in a vertical direction is identical.

A method of forming the electrical fuse matrix includes forming a seed layer on a plurality of bottom metal plates extending in a first direction; forming a plurality of poly-silicon cylinders on the seed layer; forming a spacer surrounding the plurality of poly-silicon cylinders and covering the seed layer; forming a plurality of hourglass-shaped trenches between the poly-silicon cylinders by removing a portion of the spacer; forming a plurality of anti-fuse structures in the hourglass-shaped trenches; and forming a plurality of top metal plates on the anti-fuse structures.

An electronic circuit comprises a first resistor (1) and a second resistor (2). The first resistor comprises: a first sheet (10) of resistive material; and a first pair (11, 12) of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness (LI) of the first sheet. The second resistor comprises: a second sheet (20) of resistive material; and a second pair (21, 22) of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path (L2) in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

An integrated circuit device includes a lower insulating film on a substrate, a lower metal wiring layer extending through the lower insulating film, an insulating protective structure on a top surface of each of the lower metal wiring layer and the lower insulating film, an upper insulating film on the insulating protective structure, an upper metal wiring layer on the upper insulating film, and a conductive contact plug extending through the upper insulating film and the insulating protective structure in a vertical direction and contacting each of the lower metal wiring layer and the upper metal wiring layer. The insulating protective structure includes a plurality of first silicon carbonitride (SiCN) films and at least one first oxide thin film. Each first oxide thin film is between two adjacent ones of the plurality of first SiCN films.

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

An electronic circuit comprises a first resistor and a second resistor. The first resistor comprises: a first sheet (e.g. layer or film) of resistive (i.e. electrically resistive) material; and a first pair of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness of the first sheet. The second resistor comprises: a second sheet (e.g. layer or film) of resistive material; and a second pair of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.