Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.

An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

According to one aspect of the disclosure, there is provided an integrated circuit die includes: a substrate including a front side and a back side opposite to the front side; a front structure including a first element layer on the front side of the substrate and a first wiring layer on the first element layer; and a back structure including a second element layer on the back side of the substrate and a second wiring layer on the second element layer.

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

According to one aspect of the disclosure, there is provided an integrated circuit die includes: a substrate including a front side and a back side opposite to the front side; a front structure including a first element layer on the front side of the substrate and a first wiring layer on the first element layer; and a back structure including a second element layer on the back side of the substrate and a second wiring layer on the second element layer.

A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.

A semiconductor device of the present disclosure includes: a semiconductor element disposed on a first surface side of a semiconductor substrate; a through-electrode that is provided through the semiconductor substrate in a thickness direction of the semiconductor substrate and introduces charge obtained in the semiconductor element to a second surface side of the semiconductor substrate; and an amplifier transistor that outputs an electrical signal based on the charge introduced by the through-electrode, the amplifier transistor using the through-electrode as a gate electrode and including a source region and a drain region around the through-electrode.

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

The present disclosure relates to semiconductor structures, methods for making the same, and methods using the same. The semiconductor structure comprises a first substrate, a second substrate on the first substrate, a first bonding layer between the first substrate and the second substrate, a first etch stop layer between the first bonding layer and the second substrate, and the first etch stop layer has high etch selectivity against the first bonding layer. In particular, some embodiments of the present disclosure relate to semiconductor structures with etch stop layer, methods for making the same, and methods using the same.

A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.