A piezoelectric actuator (1) includes: a piezoelectric element (3); and a first frictional portion (10) and a second frictional portion (12) that are disposed on one principal surface (2d) of the piezoelectric element (3). The first frictional portion (10) is disposed at a position other than the antinodes of the piezoelectric element (3) at which a distance from one of the end surfaces (2a) is less than ⅓ L, where L represents a length in the longitudinal direction of the piezoelectric element (3). The second frictional portion (12) is disposed at a position other than the antinodes of the piezoelectric element (3) at which a distance from the other of the end surfaces (2b) is less than ⅓ L.

A ceramic electronic component includes a ceramic body and first and second outer electrodes. The first and second outer electrodes respectively include first and second resin-containing electrode layers and first and second Ni plating layers. The first and second Ni plating layers are respectively provided on the first and second resin-containing electrode layers. When a thickness of the first or second Ni plating layer is t1 and a distance by which a portion of the first or second Ni plating layer that is in contact with the second principal surface extends in the length direction is t2, t2/t1 is less than about 1.

A sensor for obtaining downhole data includes a first piezoelectric layer. The sensor also includes a second piezoelectric layer having a trench extending a depth below a surface of the second piezoelectric layer. The sensor also includes an electrode positioned within the trench. The first piezoelectric layer is directly coupled to the second piezoelectric layer.

Disclosed is a method for manufacturing an ultrasonic transducer assembly comprising an ultrasonic transducer chip having a main surface comprising a plurality of ultrasound transducer elements and a plurality of first contacts for connecting to said ultrasound transducer elements, a contact chip having a further main surface comprising a plurality of second contacts, a backing member comprising ultrasound absorbing and/or scattering bodies, said backing member comprising a first surface on which the transducer chip is mounted and a second surface on which the contact chip is mounted. A flexible interconnect extends over said backing member from the main surface to the further main surface, the flexible interconnect comprising a plurality of conductive tracks, each conductive track connecting one of said first contacts to a second contact. An ultrasound probe including such an assembly, an ultrasonic imaging system including such an ultrasound probes and manufacturing methods of such an assembly and probe are also disclosed.

An electronic component includes external electrodes formed on an external surface of a body to be electrically connected to internal electrodes, and containing metal particles and glass, wherein the metal particles include particles having a polyhedral shape.

A multi-layer piezoelectric microactuator assembly has at least one poled and active piezoelectric layer and one poled but inactive piezoelectric layer. The poled but inactive layer acts as a constraining layer in resisting expansion or contract of the first piezoelectric layer.

Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first piezoelectric layer, and a first dummy layer. The first piezoelectric layer is over the substrate, and the first piezoelectric layer has a first top surface. The first dummy layer is over the first piezoelectric layer, and the first dummy layer has a second top surface. And an average roughness of the first top surface is greater than an average roughness of the second top surface. A method for manufacturing the semiconductor structure is also provided.

In a non-limiting embodiment, a device may include a substrate, and a hybrid active structure disposed over the substrate. The hybrid active structure may include an anchor region and a free region. The hybrid active structure may be connected to the substrate at least at the anchor region. The anchor region may include at least a segment of a piezoelectric stack portion. The piezoelectric stack portion may include a first electrode layer, a piezoelectric layer over the first electrode layer, and a second electrode layer over the piezoelectric layer. The free region may include at least a segment of a mechanical portion. The piezoelectric stack portion may overlap the mechanical portion at edges of the piezoelectric stack portion.

The present invention relates to a gate structure and a method for its production.

In particular, the present invention relates to a gate structuring of a field effect transistor (FET), wherein the field effect transistor with the same active layer can be constructed as a depletion type, or D-type, as an enhancement type, or E-type, and as a low noise type, or LN-type, on a shared substrate base using a uniform method.

The gate structure according to the invention comprises a substrate; a piezoelectric active layer (112, 212) disposed on the substrate (110, 210); a passivation layer (120, 220) disposed on the active layer (112, 212), wherein the passivation layer (120, 220) has a recess (122, 222) that extends through the entire passivation layer (120, 220) in the direction of the active layer (112, 212); a contact element (140, 240) disposed within the recess (122, 222), wherein the contact element (140, 240) extends from the active layer (112, 212) to above the passivation layer (120, 220); and a cover layer (150, 250) that covers the contact element (140, 240) above the passivation layer (120, 220); wherein at least one layer disposed above the active layer is tensile stressed or compressively stressed in the area around the contact element, with a normal tension of ||>200 MPa, wherein via the individual stresses in the area around the contact element, a resulting force on the boundary area between the passivation layer and the active layer is set, which influences via the piezoelectric effect the electron density in the active layer in the area below the contact element.