A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

A load modulation circuit of an embodiment has a first element, a switch element configured to connect the first element to an end portion of a coil, a first control section configured to control an operation of the switch element, and a second control section configured to control an amount of electric charges accumulated in the first element, and the second control section discharges the electric charges accumulated in the first element when the switch element is switched to off.

A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.

A semiconductor structure includes a substrate, a first well region on the substrate, a shallow trench isolation (STI) region over the first well region, and a first transistor. The first transistor includes a first fin formed on the first well region, a first gate electrode formed on the first fin, and a first doping region formed on the first fin. The semiconductor structure further includes a first power rail on the first well region and in the STI region and a first source/drain contact over the first doping region and the first power rail to electrically connect the first doping region to the first power rail. A bottom surface of first source/drain contact is in direct contact with the STI region.

A transistor that may provide improved durability and reliability is disclosed. The transistor includes a substrate including an active region, an element isolation film in the substrate that defines the active region, a first impurity region on a lower surface of the element isolation film, a second impurity region in the substrate, a gate electrode on the substrate and extending in a first direction, a source/drain area on at least one side of the gate electrode, a first source/drain contact group on the source/drain area, and a second source/drain contact group on the source/drain area and spaced apart from the first source/drain contact group in the first direction, wherein the second impurity region is between the first source/drain contact group and the second source/drain contact group.

A semiconductor device includes a first isolation structure corresponding to a first device region of a substrate and including a first insulating layer in a first isolation groove of the first isolation structure, and a second isolation structure corresponding to a second device region of the substrate and including a second insulating layer in a second isolation groove of the second isolation structure. The first insulating layer comprises ions.

A semiconductor device includes a substrate, a first oxide layer and a second oxide layer. The substrate has a first region and a second region. The first oxide layer is disposed on the first region. The first oxide layer includes a first thermal oxide layer and a first deposited oxide layer, and a portion of the first thermal oxide layer is formed by a pad oxide layer. The second oxide layer is disposed on the second region. The second oxide layer includes a second thermal oxide layer and a second deposited oxide layer.

A method for fabricating a semiconductor device having a substantially undoped channel region includes providing a substrate having a fin extending from the substrate. An in-situ doped layer is formed on the fin. By way of example, the in-situ doped layer may include an in-situ doped well region formed by an epitaxial growth process. In some examples, the in-situ doped well region includes an N-well or a P-well region. After formation of the in-situ doped layer on the fin, an undoped layer is formed on the in-situ doped layer, and a gate stack is formed over the undoped layer. The undoped layer may include an undoped channel region formed by an epitaxial growth process. In various examples, a source region and a drain region are formed adjacent to and on either side of the undoped channel region.

A method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 510.sup.18 dopant atoms per cm.sup.3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.