A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first gate structure of a first gate pitch, a first channel region under the first gate electrode, a first source/drain (S/D) feature contacting the first channel region and having a first S/D depth. The second transistor includes a second gate structure of a first gate pitch, a second channel region under the first gate electrode, a second S/D feature contacting the second channel region and having a second S/D depth. The second gate pitch is larger than the first gate pitch. The second S/D depth is larger than the first S/D depth.

A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a first well region, a source/drain (S/D) feature, and a pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region abuts the second surface of the substrate and has a first conducive type. The S/D feature abuts the second surface of the substrate and has a second conductivity type different from the first conductivity type. The pick-up region abuts the first surface of the substrate and has the first conductivity type.

A semiconductor device includes a first device configured to receive a first level voltage through a first terminal, and output a first output voltage through a second terminal when a gate voltage is applied through a gate terminal; a boost device configured to receive a second level voltage through a first terminal, and output a second output voltage having a higher value than the first output voltage when the first output voltage is applied as a gate voltage through a gate terminal; and a second device configured to receive a third level voltage through a first terminal, and output a third output voltage when the second output voltage is applied as a gate voltage through a gate terminal, wherein the second output voltage is greater than a threshold voltage of the second device.

A method of manufacturing a Schottky barrier diode includes: forming a first well region and a second well region adjacent to the first well region in a substrate; depositing a first dielectric layer over the first well region and the second well region; performing a first patterning operation on the first dielectric layer to cause the first dielectric layer to include a stepped shape; performing a second patterning operation on the first dielectric layer to form a gate dielectric layer of a first transistor device in the second well region; and forming a conductive layer over the first well region to obtain a Schottky barrier interface.

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an isolation region and a gate structure extending into the substrate, wherein a portion of the gate structure below a top surface of the substrate abuts the isolation region. An associated method for fabricating the semiconductor structure is also disclosed.

A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well. The first transistor includes first source terminal coupled to a first voltage supply. The second transistor includes a second source terminal coupled to the first drain terminal, and a second gate terminal coupled to a pad voltage terminal. The third and fourth transistor are in a second well. The third transistor includes a third source terminal and a third gate terminal coupled to the first voltage supply. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal being coupled to the pad voltage terminal.

In a method of fabricating at least one IC, doped regions are formed on a semiconductor wafer using a first photolithography mask, including at least one doped region of a test structure. Active regions are formed on the semiconductor wafer using a second photolithography mask, including active regions of the test structure. Electrical contacts are formed on the active regions of the test structure. Electrical resistances are measured between pairs of active regions of the test structure using the electrical contacts. At least one metric is determined indicating whether the doped regions are spatially aligned with the active regions based on the measured electrical resistances. In response to the at least one metric indicating the doped regions are spatially aligned with the active regions, completing fabrication of the at least one integrated circuit.

A semiconductor structure includes a first zone and a second zone. The first zone includes: a first transistor on a substrate; and a first isolation region in the substrate and defining a boundary of the first transistor. The second zone includes a second transistor on the substrate, wherein the second transistor includes: a second isolation region in the substrate and a gate electrode disposed over the substrate, the gate electrode partially overlapping the second isolation region; and a barrier layer below and spaced apart from the second isolation region.

A manufacturing method of a semiconductor integrated structure having a high voltage device, a low voltage device and a capacitor, includes: forming a bottom thermal oxide layer on a substrate; forming a chemical vapor deposition (CVD) oxide layer; forming a poly silicon hard mask layer; etching the poly silicon hard mask layer to form a high voltage poly silicon hard mask and a first electrode plate simultaneously; etching the CVD oxide layer and using the high voltage poly silicon hard mask and the first electrode plate as etching barrier layers to form a high voltage CVD oxide region and a capacitor CVD oxide region simultaneously; etching the bottom thermal oxide layer and using the high voltage poly silicon hard mask and the first electrode plate as the etching barrier layers to form a high voltage bottom thermal oxide region and a bottom thermal oxide region simultaneously.

A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A semiconductor layer is formed in the substrate. A portion of the semiconductor layer and a portion of the substrate are removed to form a trench in the substrate. An isolation structure is formed in the trench. After the isolation structure is formed, the semiconductor layer is removed to form a first recess in the substrate. A gate dielectric layer is formed on the substrate exposed by the first recess.