Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film. The second transistor comprises a first drain electrode; the second insulating film over the second drain electrode; a second oxide semiconductor film over the second insulating film; a second source electrode and a second drain electrode over the second oxide semiconductor film; a third insulating film over the second oxide semiconductor film, the second source electrode, and the second drain electrode; and a third gate electrode over the third insulating film. The first oxide semiconductor film partly overlaps with the second oxide semiconductor film.

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhombohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.

To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. By covering a side surface of an oxide semiconductor layer in which a channel is formed with an oxide semiconductor layer, diffusion of impurities into the inside from the side surface of the oxide semiconductor layer is prevented. By forming a gate electrode in a damascene process, miniaturization and high density of a transistor are achieved. By providing a protective layer covering a gate electrode over the gate electrode, the reliability of the transistor is increased.

An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.

First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

A change in electrical characteristics of a semiconductor device including an oxide semiconductor is prevented, and the reliability of the semiconductor device is improved. An oxide semiconductor is formed over a substrate; an insulator is formed over the oxide semiconductor; a metal oxide is formed over the insulator; a conductor is formed over the metal oxide; a portion of the oxide semiconductor is exposed by removing the conductor, the metal oxide, and the insulator over the oxide semiconductor; plasma treatment is performed on a surface of the exposed portion of the oxide semiconductor; and a nitride insulator is formed over the exposed portion of the oxide semiconductor and over the conductor. The plasma treatment is performed in a mixed atmosphere of an argon gas and a nitrogen gas.

An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhombohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.