An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.

A semiconductor device includes a semiconductor structure forming a carrier channel, a barrier layer arranged in proximity with the semiconductor structure, and a set of electrodes for providing and controlling carrier charge in the carrier channel. The barrier layer is at least partially doped by impurities having a conductivity type opposite to a conductivity type of the carrier channel. The material of the barrier layer has a bandgap and thermal conductivity larger than a bandgap and thermal conductivity of material in the semiconductor structure.

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.

An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.