A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

A microelectronic device includes a substrate, at least two doped well regions, an epitaxial structure, and at least two power elements. The doped well regions are disposed in the substrate, and are spaced apart from each other. Each of the doped well regions has a doping type opposite to that of the substrate. The epitaxial structure is disposed on the substrate, and is in contact with the doped well regions. The power elements are disposed on the epitaxial structure opposite to the substrate, and are cascade connected with each other. A low potential terminal of each of the power elements is electrically connected to a respective one of the doped well regions. A method for making the microelectronic device is also provided.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.