The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.

The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector region above a semiconductor substrate; a base region above the collector region; an emitter region adjacent to the base region; and an undercut structure above the semiconductor substrate and adjacent to the collector region.

A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.

In a method of forming a bipolar junction transistor (BJT) structure, an emitter/base/collector structure is formed, comprising mutually parallel fins with an insulator material disposed between the fins. Each fin of the emitter/base/collector structure has first and second peripheral regions doped with a first doping type on opposite sides of a central region doped with a second doping type opposite the first doping type. The first peripheral regions of the fins are an emitter of the BJT structure, the central regions of the fins are a base of the BJT structure, and the second peripheral regions of the fins are a collector of the BJT structure. Continuous emitter, base, and collector contact strips are epitaxially deposited on the emitter, base, and collector of the BJT structure, respectively.

A bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor.