Method for Fabricating a High Voltage Breakdown Resistant Bipolar Transistor

Abstract

A bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor.

Claims

1. A method for fabricating a bipolar transistor, the method comprising: forming a sub-collector in a semiconductor substrate, said sub-collector being doped with a first dopant type; forming a device layer doped with said first dopant type over said sub-collector; patterning a trench in said device layer, said trench bordering a collector of said bipolar transistor; implanting a dopant of a second dopant type opposite said first dopant type into said device layer through said trench; forming a shallow trench isolation (STI) in said trench; forming a Reduced Surface Layer (RESURF) region having said second dopant type between said collector and said STI; wherein said RESURF region protects against breakdown of said bipolar transistor.

2. The method of claim 1, wherein said forming said RESURF region comprises annealing said dopant of said second type implanted into said device layer through said trench.

3. The method of claim 1, further comprising forming a collector sinker region doped with said first dopant type electrically coupled to said sub-collector, wherein said RESURF region extends under said STI and retards diffusion of dopants from said collector sinker region.

4. The method of claim 1, wherein said dopant of said second type is implanted into said device layer through said trench using an ion implantation energy of less than one hundred kilo-electron volts (100 keV) and an implantation concentration of less than 910.sup.12 cm.sup.2.

5. The method of claim 1, wherein said first dopant type is N type and said second dopant type is P type.

6. The method of claim 5, wherein said sub-collector is arsenic (AS) doped and said collector is phosphorus (P) doped.

7. The method of claim 5, wherein said RESURF region is boron (B) doped.

8. The method of claim 1, wherein said first dopant type is P type and said second dopant type is N type.

9. The method of claim 1, wherein said bipolar transistor is a silicon only bipolar transistor.

10. The method of claim 1, wherein said bipolar transistor is a silicon germanium (SiGe) bipolar transistor.

11. The method of claim 1, wherein a breakdown voltage of said bipolar transistor is increased by up to three volts (3V).

12-20. (canceled)

21. A method for fabricating a bipolar transistor, the method comprising: forming a sub-collector in a semiconductor substrate, said sub-collector being doped with a first dopant type; forming a device layer doped with said first dopant type over said sub-collector; patterning a trench in said device layer; implanting a dopant of a second dopant type opposite said first dopant type into said device layer through said trench; forming a shallow trench isolation (STI); forming a Reduced Surface Layer (RESURF) region having said second dopant type adjacent said collector; wherein said RESURF region protects against breakdown of said bipolar transistor.

22. The method of claim 21, wherein said forming said RESURF region comprises annealing said dopant of said second type implanted into said device layer through said trench.

23. The method of claim 21, further comprising forming a collector sinker region doped with said first dopant type electrically coupled to said sub-collector.

24. The method of claim 23, wherein said RESURF region extends under said STI and retards diffusion of dopants from said collector sinker region.

25. The method of claim 21, wherein said dopant of said second type is implanted into said device layer through said trench using an ion implantation energy of less than one hundred kilo-electron volts (100 keV) and an implantation concentration of less than 910.sup.12 cm.sup.2.

26. The method of claim 21, wherein said first dopant type is N type and said second dopant type is P type.

27. The method of claim 26, wherein said sub-collector is arsenic (AS) doped and said collector is phosphorus (P) doped.

28. The method of claim 26, wherein said RESURF region is boron (B) doped.

29. The method of claim 21, wherein said bipolar transistor is a silicon germanium (SiGe) bipolar transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 shows a flowchart presenting an exemplary method for fabricating a high voltage breakdown resistant bipolar transistor, according to one implementation of the present application.

[0005] FIG. 2 shows a cross-sectional view of an exemplary structure corresponding to an initial fabrication action according to the flowchart of FIG. 1.

[0006] FIG. 3 shows a cross-sectional view of the exemplary structure of FIG. 2 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0007] FIG. 4 shows a cross-sectional view of the exemplary structure of FIG. 3 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0008] FIG. 5 shows a cross-sectional view of the exemplary structure of FIG. 4 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0009] FIG. 6 shows a cross-sectional view of the exemplary structure of FIG. 5 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0010] FIG. 7 shows a cross-sectional view of the exemplary structure of FIG. 6 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0011] FIG. 8 shows a cross-sectional view of the exemplary structure of FIG. 7 at a subsequent fabrication action according to the flowchart of FIG. 1.

[0012] FIG. 9 shows a cross-sectional view of an exemplary structure fabricated according to the flowchart of FIG. 1, according to another implementation.

DETAILED DESCRIPTION

[0013] The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a manner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.

[0014] As stated above, in very high breakdown bipolar transistors used in power amplifiers, such as devices designed to withstand reverse bias voltages between the collector and base in the fifteen to thirty volt (15V-30V) range, non-traditional breakdown mechanisms may be observed. For example, and as also stated above, despite reduction of dopant concentration in the collector to better sustain high voltage operation, lateral breakdown can occur. Unfortunately, however, conventional techniques for rendering a bipolar transistor more voltage tolerant have proved substantially ineffective in preventing lateral breakdown, while undesirably reducing speed.

[0015] The present application is directed to high voltage breakdown resistant bipolar transistors (hereinafter simply bipolar transistors) and methods for their fabrication that address and overcome the problems in the art described above. In one implementation, such a bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor. In various implementations, the breakdown voltage of such a device may be increased by up to three volts (3V) when compared with traditional bipolar transistors used in power amplifier applications, with a substantially negligible reduction in device speed.

[0016] FIG. 1 illustrates flowchart 100 of an exemplary method for forming a bipolar transistor, according to one implementation of the present application. Actions 101 through 107 shown in flowchart 100 of FIG. 1 are sufficient to describe one implementation of the present inventive concepts. Other implementations of the present inventive concepts may utilize actions different from those shown in flowchart 100. Certain details and features have been left out of flowchart 100 that are apparent to a person of ordinary skill in the art. For example, an action may consist of one or more sub-actions or may involve specialized equipment or materials, as known in the art.

[0017] Moreover, some actions, such as masking and cleaning actions, are omitted so as not to distract from the illustrated actions.

[0018] With respect to FIGS. 2, 3, 4, 5, 6, 7, and 8 (hereinafter FIGS. 2-8), structures 201, 202, 203, 204, 205, 206, and 207 shown respectively in FIGS. 2-8 illustrate the result of performing the method of flowchart 100, according to one implementation. For example, FIG. 2 provides a cross-sectional view of structure 201 including semiconductor substrate 210 in which N+ sub-collector 212 is formed (action 101).

[0019] Structure 202, in FIG. 3, is a cross-sectional view of structure 201 after formation of N type device layer 214 over N+ sub-collector 212 (action 102). Structure 203, in FIG. 4, is a cross-sectional view of structure 202 after trenches 216 are patterned in device layer 214 (action 103), and so forth.

[0020] It is noted that the cross-sectional structures shown in FIGS. 2-8 are provided as specific implementations of the present inventive principles, and are shown with such specificity for the purposes of conceptual clarity. Consequently, particular details such as the materials used to form the cross-sectional structures shown in FIGS. 2-8, as well as the techniques used to produce the various depicted features, are being provided merely as examples, and should not be interpreted as limitations.

[0021] Referring to flowchart 100 in FIG. 1, in combination with FIG. 2, flowchart 100 begins with forming sub-collector 212 in semiconductor substrate 210, sub-collector 212 being doped with a first dopant type (action 101). Semiconductor substrate 210 may be an undoped silicon substrate, for example. As shown in FIG. 2, according to one exemplary implementation, semiconductor substrate includes N+ sub-collector formed therein. It is noted that although FIGS. 2-8 depict fabrication of an NPN bipolar transistor, that representation is provided merely as an example. In other implementations, a PNP bipolar transistor may be fabricated according to the present concepts through reversal of the dopant types depicted in FIGS. 2-8. Thus, in the case of a PNP bipolar transistor, action 101 for example, can correspond to forming a P+ sub-collector in semiconductor substrate 210.

[0022] Referring once again to the exemplary implementations in which an NPN bipolar transistor is fabricated, N+ sub-collector 212 may be formed in semiconductor substrate 210 through ion implantation and diffusion of N type dopants to form N+ sub-collector 212. For example, arsenic (As) may be implanted into semiconductor substrate and may be thermally driven to form N+ sub-collector 212 having a dopant concentration of approximately 10.sup.19cm.sup.3to 10.sup.20cm.sup.3.

[0023] Moving to structure 202 in FIG. 3, with continued reference to flowchart 100, in FIG. 1, flowchart 100 continues with forming device layer 214 doped with the first dopant type (e.g., N type) over sub-collector 212 (action 102). Device layer 214 may be, for example, a silicon layer or a silicon-germanium (SiGe) layer. Thus, in various implementations the bipolar transistor fabricated according to the method outlined by flowchart 100 in FIG. 1, may be a silicon only bipolar transistor, or a SiGe bipolar transistor.

[0024] Device layer 214 may be formed using any suitable techniques known in the art. For example, device layer may be deposited or epitaxially grown using one of chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). Alternatively, in some implementations, it may be advantageous or desirable to form device layer 214 using one of atomic layer deposition (ALD) or low energy plasma-enhanced chemical vapor deposition (LEPECVD).

[0025] According to the exemplary NPN bipolar transistor implementation shown in FIGS. 2-8, device layer 214 may be N type doped through ion implantation and diffusion of N type dopants. For example, phosphorus (P) may be implanted into device layer and may be annealed to form N type device layer 214 having a dopant concentration of approximately 10.sup.17cm.sup.3to 10.sup.18cm.sup.3.

[0026] Continuing to structure 203 in FIG. 4, with continued reference to flowchart 100 in FIG. 1, flowchart 100 continues with patterning trenches 216 in device layer 214, where trenches 216 border respective collectors 220 of bipolar transistors undergoing fabrication according to the method outlined by flowchart 100 (action 103). Also shown in FIG. 4 is patterning mask 218 situated over and shielding portions of device layer 214 during the patterning of trenches 216. It is noted that patterning mask 218 may include a composite structure including a nitride stack having silicon dioxide (SiO.sub.2) and silicon nitride (Si.sub.XN.sub.Y) layers, which may be deposited or thermally grown, overlaid by photoresist, for example.

[0027] Trenches 216 may be patterned in device layer 214 using any suitable techniques typically utilized in the art, such as an ion-reactive dry etching process, for example. As shown in FIG. 4, trenches 216 border and partially define collectors 220 within device layer 214. As noted above, according to the exemplary implementations shown by FIGS. 2-8, device layer 214 may be N type phosphorus doped to a dopant concentration of approximately 10.sup.17cm.sup.3to 10.sup.18cm.sup.3. Consequently, collectors 220 defined within device layer 214 and having such a dopant concentration are one to two orders of magnitude less heavily doped than typical bipolar transistor collectors.

[0028] Continuing to structure 204 in FIG. 5, with continued reference to flowchart 100 in FIG. 1, flowchart 100 continues with implanting dopant 222 of a second dopant type opposite the first dopant type into device layer 214 through trenches 216 (action 104).

[0029] According to the exemplary implementation shown in FIGS. 2-8, in which the first dopant type used to dope sub-collector 212 and device layer 214 is N type, the second dopant type implanted in action 104 is P type. For example, boron (B) dopant 222 may be implanted into device layer 214 through trenches 216 using an ion implantation energy of less than one hundred kilo-electron volts (100 keV) and an implantation concentration of less than 910.sup.12 cm.sup.2.

[0030] It is noted that although the implementation shown in FIGS. 2-8 depicts fabrication of an NPN bipolar transistor in which the first dopant type used to dope sub-collector 212 and device layer 214 is N type, and the second dopant type implanted in action 104 is P type, in implementations in which a PNP bipolar transistor is fabricated according to the present concepts, the first dopant type used to dope sub-collector 212 and device layer 214 may be P type, and the second dopant type implanted in action 104 may be N type.

[0031] Continuing to structure 205 in FIG. 6, with continued reference to flowchart 100 in FIG. 1, flowchart 100 continues with forming a shallow trench isolations (STI) 224 in each of trenches 216 (action 105). STIs 224 may be formed by filling trenches 216 with a dielectric material, such as silicon dioxide, using CVD for example, followed by a chemical mechanical planarization (CMP) process to remove any excess dielectric material from the surface of device layer 214.

[0032] FIG. 6 also shows patterning mask 218 as having been removed to expose collector sinker mesas 226 and base mesas 230. It is noted that each of base mesas 230 will subsequently have a respective base of the bipolar transistors being fabricated in the process outlined by flowchart 100 situated thereon. It is further noted that each of collector sinker mesas 226 will subsequently have a respective collector sinker contact of the bipolar transistors being fabricated in the process outlined by flowchart 100 situated thereon.

[0033] Continuing to structure 206 in FIG. 7, with continued reference to flowchart 100 in FIG. 1, flowchart 100 continues with forming RESURF regions 228 having the second dopant type between collectors 220 and STIs 224 (action 106). RESURF regions 228 may be formed through annealing of dopant 222 implanted into device layer 214 through trenches 216 in action 104.

[0034] Continuing to structure 207 in FIG. 8, with continued reference to flowchart 100 in FIG. 1, flowchart 100 continues with forming collector sinker regions 232 doped with the first dopant type and electrically coupled to sub-collector 212 (action 107). According to the exemplary implementation shown by FIGS. 2-8, collector sinker regions 232 are formed as N+ regions of device layer 214 through additional ion implantation and thermal diffusion of N type dopants in collector-sinker regions 232 of device layer 214. For example, phosphorus (P) may be implanted into device layer 214 and may be annealed to form N+ collector sinker regions 232 having a dopant concentration of approximately 10.sup.19cm.sup.3to 10.sup.20cm.sup.3.

[0035] It is noted once again that although FIGS. 2-8 depict fabrication of an NPN bipolar transistor, that representation is provided merely as an example. In other implementations, a PNP bipolar transistor may be fabricated according to the present concepts. Thus, in the case of a PNP bipolar transistor, action 107 for example, can correspond to forming a P+ collector sinker region in device layer 214.

[0036] Referring to FIG. 9, FIG. 9 shows a cross-sectional view of exemplary structure 240 fabricated according to the flowchart of FIG. 1, according to another implementation. As shown by comparison of FIG. 9 with FIG. 8, structure 240 differs from structure 207 in the extent to which collector sinker regions 232 diffuse beneath RESURF regions 228. That is to say, according to the exemplary implementation shown in FIG. 9, collector sinker regions 232 may extend laterally under at least a portion of RESURF regions 228.

[0037] RESURF regions 228, which are counter-doped relative to collectors 220 and situated between collectors 220 and STIs 224, protect against breakdown of the bipolar transistors in several ways. For example, the interposition of RESURF regions 228 between collectors 220 and STIs 224 can advantageously inhibit impact ionization breakdown. Moreover, and as shown in FIGS. 8 and 9, RESURF regions 228 may extend under STIs 224 and thereby advantageously retard diffusion of dopants from collector sinker regions 232 into collectors 220. As a result, in various implementations, the breakdown voltage of a bipolar transistor fabricated according to the method outlined by flowchart 100 may be increased by up to three volts (3V) when compared with traditional bipolar transistors used in power amplifier applications. By way of a specific example, bipolar transistors capable of withstanding reverse bias voltages between the collector and base in the 15V-30V range can have those sustainable voltages raised to as much as the 18V-33V range when fabricated according to the present concepts.

[0038] Thus, the present application discloses bipolar transistors and methods for their fabrication that address and overcome deficiencies in the conventional art. The concepts disclosed herein advance the state-of-the-art by providing a RESURF region counter-doped relative to the collector of a bipolar transistor and situated between the collector and an adjacent STI. The RESURF region protects against breakdown of the bipolar transistor by increasing its breakdown voltage, while advantageously having a substantially negligible impact on device speed.

[0039] From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described above, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.