In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.

A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.

Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

A method includes: receiving a composite substrate including a first region and a second region, the composite substrate including a semiconductor substrate and an insulator layer over the semiconductor substrate; forming a trench through the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench and over an upper surface of the second region; thickening the initial epitaxial layer to form an epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.