A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Embodiments of the present invention may provide a semiconductor device capable of covering the entire surface of a dielectric layer by increasing continuity while maintaining a thickness of an upper electrode of a capacitor, and a method of manufacturing the same. In addition, embodiments of the present invention may provide a semiconductor device capable of alleviating bending of a lower electrode and a method of manufacturing the same. According to the present invention, a semiconductor device comprises a lower electrode structure formed over a substrate; a dielectric layer formed over the lower electrode structure; and an upper electrode structure formed on the dielectric layer and including a silicon-containing amorphous layer in contact with the dielectric layer.

A semiconductor device includes an active pattern extending in a first horizontal direction and including a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions, the first source/drain region including a first region and a second region between the channel region and the first region, a metal-semiconductor compound layer on the first region of the first source/drain region of the active pattern, a bit line extending in a vertical direction and contacting the active pattern, and a gate electrode vertically overlapping at least a portion of the channel region of the active pattern and extending in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, wherein a first length of the first region in the first horizontal direction is greater than a second length of the second region in the first horizontal direction.

A method for fabricating a semiconductor device includes forming a mold stack including mold layers and a lower supporter layer over a substrate; forming lower electrodes having lower and upper portions in the mold stack; exposing the lower electrodes by recessing an upper surface of the mold stack; forming trimmed portions by trimming the exposed upper portions of the lower electrodes; forming a pyrolytic layer surrounding lower sides of the trimmed portions; forming a supporter liner layer over the pyrolytic layer and the trimmed portions; forming a horizontal level gap by removing the pyrolytic layer; forming an upper supporter layer over the supporter liner layer; forming a supporter hole by etching the upper supporter layer and the supporter liner layer; and exposing the outer walls of the lower portions of the lower electrodes by removing the mold layers through the supporter hole and the horizontal level gap.

A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.

Embodiments of the present invention may provide a semiconductor device capable of covering the entire surface of a dielectric layer by increasing continuity while maintaining a thickness of an upper electrode of a capacitor, and a method of manufacturing the same. In addition, embodiments of the present invention may provide a semiconductor device capable of alleviating bending of a lower electrode and a method of manufacturing the same. According to the present invention, a semiconductor device comprises a lower electrode structure formed over a substrate; a dielectric layer formed over the lower electrode structure; and an upper electrode structure formed on the dielectric layer and including a silicon-containing amorphous layer in contact with the dielectric layer.

Embodiments of the present invention may provide a semiconductor device capable of covering the entire surface of a dielectric layer by increasing continuity while maintaining a thickness of an upper electrode of a capacitor, and a method of manufacturing the same. In addition, embodiments of the present invention may provide a semiconductor device capable of alleviating bending of a lower electrode and a method of manufacturing the same. According to the present invention, a semiconductor device comprises a lower electrode structure formed over a substrate; a dielectric layer formed over the lower electrode structure; and an upper electrode structure formed on the dielectric layer and including a silicon-containing amorphous layer in contact with the dielectric layer.

A semiconductor device may include a substrate, a bit line extending in a direction perpendicular to the substrate, a plurality of semiconductor patterns having a first end portion connected to the bit line, and extending in a first direction, a first electrode having a first end portion connected to the semiconductor pattern, and extending in the first direction, and a support portion fixing a second end portion of the first electrode, where the second end portion of the first electrode is located within the support portion.