INTEGRATED CIRCUIT INCLUDING AT LEAST ONE CAPACITIVE ELEMENT AND CORRESPONDING MANUFACTURING METHOD

Abstract

A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.

Claims

1. A method for manufacturing an integrated circuit including a capacitive element, comprising manufacturing the capacitive element by: forming a first portion of a first electrode of the capacitive element by depositing a first conductive layer over a front face of a substrate and etching to define an outline of the first conductive layer; forming a low voltage dielectric layer covering the first conductive layer; depositing a second conductive layer over the front face and over the first conductive layer covered by the low voltage dielectric layer; first etching to define the second conductive layer to cover the first conductive layer and the front face of the substrate surrounding the outline of the first conductive layer; second etching to electrically separate the second conductive layer into a first portion located on a central zone of the first conductive layer to provide a second electrode of the capacitive element and a second portion comprising an inner border part located over the upper surface of the first conductive layer and surrounding the first portion and an outer border part located over the front face of the substrate and surrounding the first conductive layer to provide a second portion of the first electrode; and forming an electrical connection between the first conductive layer and the second portion of the second conductive layer.

2. The method according to claim 1, wherein second etching is configured to etch an annular opening through the entire thickness of the second conductive layer until reaching the first conductive layer, said annular opening separating the first portion of the second conductive layer inside the shape of the annual opening from the second portion of the second conductive layer outside the shape of the annular opening.

3. The method according to claim 1, further comprising, prior forming the first electrode, forming an isolation region in the substrate of the shallow trench isolation type, wherein said first electrode is formed on the isolation region.

4. The method according to claim 1, wherein the low voltage dielectric layer is formed by a silicon oxide layer having a thickness comprised between 1 nanometer and 6 nanometers.

5. The method according to claim 1, further comprising manufacturing a low voltage transistor supported by the substrate and configured for operation at voltages below 5V, and wherein forming the low voltage dielectric layer is made at a same time as forming a gate dielectric layer of the low voltage transistor.

6. The method according to claim 1, further comprising manufacturing a low voltage transistor supported by the substrate and configured to operate at voltages below 5V, and wherein depositing the second conductive layer is made at a same time as depositing a gate conductive layer of the low voltage transistor, and wherein second etching of the second conductive layer is made at a same time as etching a gate conductive layer defining a gate region of the low voltage transistor.

7. The method according to claim 1, further comprising manufacturing a high voltage transistor supported by the substrate and configured to operate at high voltages greater than 5V, and wherein forming the first electrode is made at a same time forming a gate region of the high voltage transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Other advantages and features of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings, in which:

[0047] FIG. 1 illustrates sectional views of embodiments of capacitive elements of the MIM type;

[0048] FIGS. 2 and 3 illustrate an embodiment of a capacitive element; and

[0049] FIGS. 4A to 4I illustrate steps and results of steps of a method for manufacturing the capacitive element CPP shown in FIGS. 2 and 3.

DETAILED DESCRIPTION

[0050] FIGS. 2 and 3 illustrate an advantageous exemplary embodiment of a capacitive element CPP of an integrated circuit CI.

[0051] The capacitive element CPP may for example belong to a radiofrequency (RF) communication circuit of the integrated circuit CI, for example in a filtering circuit of an RF reception chain; or in an analog portion of the integrated circuit CI, for example in a compensation circuit or as a decoupling capacitor.

[0052] FIG. 2 illustrates a sectional view of the capacitive element CPP, in an xz plane of a reference mark (xyz), substantially at the position II-II of FIG. 3.

[0053] FIG. 3 illustrates a top view of the capacitive element CPP, in a xy plane of the reference mark (xyz), substantially at the position III-III of FIG. 2.

[0054] The capacitive element CPP comprises a superposition of a first conductive armature P1 of a first electrode E1, of a dielectric interface GO, and of a second conductive armature P2int of a second electrode E2.

[0055] It is considered that an electrode includes the corresponding conductive armature and an electrode terminal, formed for example in metal levels of an interconnection portion of the integrated circuit, provided for coupling the capacitive element with the circuit to which it is intended.

[0056] This superposition is disposed in the order given above, starting on a front face FA of a semiconductor substrate PSUB of the integrated circuit CI. The surface of the front face FA, on which the capacitive element CPP is disposed, is fully included in the upper surface, in the plane of the front face FA, of an isolation region STI of the shallow trench isolation type.

[0057] The shallow trench isolations are typical elements allowing laterally isolating wells or active regions of the substrate PSUB. The shallow trench isolations STI are conventionally formed by etching openings called trenches in the substrate PSUB, a filling of the trenches with a dielectric material, typically silicon oxide, and by polishing the excess dielectric until uncovering the front face FA.

[0058] Thus, the capacitive element CPP is an MIM type realization (for Metal-Oxide-Metal generalized by extension to conductor-insulator-conductor structures), thus having a good linearity of the capacitive value relative to the applied voltage. Furthermore, the MIM-type capacitive element CPP does not have in particular a connection with the semiconductor substrate PSUB, which may broadcast interfering signals or require bulky insulation semiconductor structures of the triple-well type.

[0059] The first armature includes a first conductive layer P1 made of polycrystalline silicon, thus disposed on the isolation region STI at the front face FA.

[0060] The first conductive layer P1 is delimited by the outline thereof P1cntr, rectangular in shape in FIG. 3, but may have another shape allowing occupying an available surface in the integrated circuit, sometimes called a filling capacitor in this regard.

[0061] For example, the first conductive layer P1 may have the same composition and the same thickness as a gate conductive region HVG (FIG. 4I) of a high or medium voltage transistor MOS HV-MV (FIG. 4I) of the integrated circuit intended for operate at high or medium voltages greater than 5V.

[0062] The first conductive layer P1 can also have the same composition and the same thickness as a floating gate conductive region of a floating gate transistor of a memory cell NVMcell (FIG. 4I) of the integrated circuit.

[0063] The dielectric interface includes a low voltage dielectric layer GO covering the first conductive layer P1.

[0064] The term low voltage dielectric layer means a dielectric layer having a breakdown voltage adapted to a low voltage domain of the integrated circuit, but not to a high voltage domain.

[0065] The terms low voltage and high voltage are thus defined in a relative manner with respect to the voltages involved in the integrated circuit. For example, the low voltages can be voltages in the range of 1V to 2V, or more broadly, voltages below 5V with a tolerance margin, while the high voltages can be voltages in the range of 12V, or more broadly voltages comprised between 5V and 20V.

[0066] For example, the low voltage dielectric layer GO is a silicon oxide layer having a thickness comprised between 1 nanometers and 6 nanometers.

[0067] Also, the low voltage dielectric layer GO can advantageously have the same composition and the same thickness as a gate dielectric layer GO of a low voltage transistor MOS LV (FIG. 4I) of the integrated circuit intended to operate at low voltages below 5V.

[0068] In fact, one can differentiate two types of low voltage transistor, having respective gate dielectric layers of different thicknesses.

[0069] For example, a first low voltage dielectric thickness GO1, for example in the range of 2 nm, corresponds in particular to logic circuit transistors intended to operate at voltages below 1.5V.

[0070] For example, a second low voltage dielectric thickness GO2, for example in the range of 5 nm, corresponds in particular to input/output interface circuit transistors intended to operate at voltages comprised between 2V and 5V.

[0071] Finally, the second armature includes a first portion P2int of a second conductive layer P2 made of polycrystalline silicon, disposed on the dielectric layer GO, and positioned in a central zone of the first conductive layer P1.

[0072] The term central zone means a surface located inside the shape delimited by the outline P1cntr of the first conductive layer P1. For example, the central zone can be delimited according to the shape of a homothetic reduction in the shape of the outline P1cntr of the first conductive layer P1.

[0073] For example, the second conductive layer P2 may have the same composition and the same thickness as a conductive region of the gate of the low voltage transistor MOS LV (FIG. 4I) of the integrated circuit.

[0074] The second conductive layer P2 can also have the same composition and thickness as a control gate conductive region of a floating gate transistor of a memory cell NVMcell (FIG. 4I) of the integrated circuit.

[0075] Furthermore, a second portion P2ext of the same second conductive layer P2 is disposed over the entire outline P1cntr of the first conductive layer P1.

[0076] Indeed, the second portion P2ext of the second conductive layer P2 is located, on the one hand, on the upper surface of the first conductive layer P1, on the inner border brdr_int of the entire outline of the first conductive layer P1cntr, and on the other hand, on the front face FA, on the outer border brdr_ext of the entire outline of the first conductive layer P1cntr.

[0077] The second portion P2ext of the second conductive layer P2 thus surrounds the first conductive layer P1, in the form of a staircase, thus encompassing the ridges and the vertices located over the entire contour P1cntr of the first conductive layer P1.

[0078] The first conductive layer P1 and the second portion of the second conductive layer P2ext are electrically connected, so as to have a potential difference which is always zero therebetween.

[0079] For example, contact pillars CT1P1 can link the first conductive layer P1 to a terminal of the first electrode E1, and contact pillars CT1P2 can link the second portion P2ext of the second conductive layer P2 to the terminal of the first electrode E1, in order to connect the first conductive layer P1 with the second portion P2ext.

[0080] Similarly, the first portion P2int of the second conductive layer P2 can be electrically connected to a terminal of the second electrode E2 by contact pillars CT2P2.

[0081] An annular opening OUV is formed through the entire thickness of the second conductive layer P2 until reaching the first conductive layer P1, on the one hand, in order to electrically separate the first portion P2int and the second portion P2ext of the second conductive layer P2.

[0082] Thus, the first portion of the second conductive layer P2int is located inside the ring shape of the opening OUV and the second portion of the second conductive layer P2ext is located outside the ring shape of the opening OUV.

[0083] The ring shape of the opening OUV is a rectangular ring in the representation of FIG. 3. The terms ring and annular designate a geometrical area delimited by an inner perimeter and an outer perimeter which are parallel to each other, and parallel to the outline of the first conductive layer P1cntr. In other words, the annular opening can be materialized by a strip running along the outline P1cntr at a distance offset inwardly, the offset corresponding to said inner border brdr_int.

[0084] On the other hand, the opening formed in the second conductive layer P2 gives access to the first conductive layer P1, in particular to connect the contact pillars CT1P1 thereto.

[0085] Finally, the structure of the capacitive element CPP can be made such that the low voltage dielectric layer GO is completely covered until the formation of said annular opening OUV. The low voltage dielectric layer GO is therefore protected during wet etching steps. Reference is made in this regard to FIGS. 4A to 4I.

[0086] FIGS. 4A to 4I illustrate steps and results of steps of an example of a method for manufacturing the capacitive element CPP (GO) of an integrated circuit CI, as previously described in relation to FIGS. 2 and 3.

[0087] In addition to the manufacture of the capacitive element CPP (GO), FIGS. 4A to 4I illustrate steps of manufacturing other elements of the integrated circuit, which are implemented in conjunction with the steps of manufacturing the capacitive element CPP.

[0088] In this example, the other elements of the integrated circuit CI include non-volatile memory cells NVMcell, a high voltage capacitive element CP1P2 (ONO), high and medium voltage transistors MOS HV-MV and low voltage transistors MOS LV.

[0089] For brevity, reference will be made to the high and medium voltage transistors as high voltage transistors.

[0090] The manufacture of the capacitive element CPP can be cointegrated with the manufacture of only some of the other integrated circuit elements which are exemplified herein. In particular, the presence of the high voltage capacitive element CP1P2 (ONO) is not necessary for the cointegration, and for example, the presence of the memory cells NVMcell and the low voltage transistors MOS LV as well as the high and medium voltage transistors MOV HV-MV may be sufficient for a complete cointegration of the manufacture of the capacitive element CPP (GO).

[0091] FIG. 4A illustrates the result 410 of forming shallow isolation regions STI, particularly in the regions accommodating the capacitive elements CPP (GO) and CP1P2 (ONO) to avoid forming a capacitive interface with the semiconductor substrate PSUB, but also in the other regions to form typical lateral isolation regions.

[0092] Further, an implantation of a triple well TRPW has been performed in the region of the memory cell NVMcell and an implantation of a high voltage well HVW has been performed in the region of the high voltage transistors MOS HV-MV.

[0093] Vertical gate regions TRCH of buried access transistors have been formed in open trenches in the triple well TRPW of the region of the memory cells NVMcell.

[0094] A high voltage dielectric layer HVOX has been formed, for example by thermal growth, over the entire front face FA of the substrate PSUB except in the portion of the memory cells NVMcell where the thickness of the dielectric has been reduced to a thickness called tunnel TNOX associated with the tunnel oxide layer of the memory cell transistor.

[0095] Finally, a first conductive layer P1, for example made of polycrystalline silicon, has been deposited on all regions of the integrated circuit.

[0096] The first conductive layer P1 will form floating gates in the portion of the memory cells NVMcell, first armatures of the capacitive elements CPP (GO), CP1P2 (ONO), and gates of the high voltage transistors MOS HV-MV.

[0097] FIG. 4B illustrates an etching 420 of the first conductive layer P1, allowing removing the first conductive layer P1 from the region of the low voltage transistors MOS LV, and defining the position and the shape of the gate structures of the high voltage transistors MOS HV-MV, as well as a first armature of the high voltage capacitive element CP1P2 (ONO).

[0098] The etching 420 also allows defining the outline P1cntr of the first frame of the capacitive element CPP (GO).

[0099] The etching 420 uses a photolithographed mask M20 defining the zones which are exposed or not to a directional etching, typically a plasma-type dry etching.

[0100] FIG. 4C illustrates the result 430 of implanting a low voltage well LVW in the portion of the low voltage transistors LV MOS and forming of a dielectric layer ONO. The dielectric layer ONO typically includes a superposition of oxide, nitride, and silicon oxide layers formed over all regions of the integrated circuit. The formation of the dielectric layer ONO is isotropic, that is to say that the growth of the layer is of a thickness which is substantially equal regardless of the orientation of the surface on which the growth is made.

[0101] The dielectric layer ONO allows in particular forming a dielectric thickness having a breakdown voltage greater than high voltages involved in the operation of the integrated circuit CI, in particular in the region of the memory cells NVMcell and the region of the high voltage capacitive element CP1P2 (ONO). Furthermore, the dielectric layer ONO allows constituting a stop layer for etchings of the second conductive layer P2 (see FIG. 4G).

[0102] FIG. 4D illustrates a step of removing 440 of the dielectric layer ONO, in particular in the region of the low voltage transistors MOS LV and in the region of the capacitive element CPP (GO). The removal step 440 uses a photolithographed mask M40, defining the zones which are exposed or not to a directional etching.

[0103] The etching being typically provided to remove a flat dielectric thickness ONO, a remainder of a vertical overthickness (in the direction of the etching) may be present on the flanks of the first armature P1 of the capacitive element CPP (GO) forming a spacer SP in a manner comparable to gate spacers.

[0104] FIG. 4E illustrates a formation 450 of a low voltage dielectric layer GO over all regions of the integrated circuit.

[0105] The formation 450 of the low voltage dielectric layer GO is also isotropic and covers in particular the entire first armature P1 of the capacitive element CPP (GO).

[0106] The low voltage dielectric layer GO is intended in particular to form gate dielectrics of the low voltage transistors MOS LV.

[0107] In this regard, depending on the type of formed transistor and the voltage domain for which they are intended, the low voltage dielectric layer GO may have a first thickness GO1, for example comprised between 1 nm and 3 nm, for voltages below 1.5V. An additional dielectric layer GO2 can be formed over the layer GO1, to form a greater cumulative thickness, for example comprised between 3 nm and 6 nm, for voltages below 5V.

[0108] FIG. 4F illustrates a formation 460 of a second conductive layer P2, for example made of polycrystalline silicon, deposited on all regions of the integrated circuit.

[0109] The second conductive layer P2 will form control gates in the portion of the memory cells NVMcell, second armatures of the capacitive elements CPP (GO), CP1P2 (ONO), and gates of the low voltage transistors MOS LV.

[0110] FIG. 4G illustrates a first etching 470 of the second conductive layer P2, allowing removing the second conductive layer P2 from the region of the high voltage transistors MOS HV-MV, and defining the extent of a second armature of the high voltage capacitive element CP1P2 (ONO).

[0111] The high voltage capacitive element CP1P2 (ONO) thus formed may correspond to the conventional example 11 of FIG. 1.

[0112] The first etching 470 of the second conductive layer P2 further allows defining the extent of the second conductive layer P2 in the region of the capacitive element CPP (GO), so as to completely cover the first conductive layer P1 and to overflow on the front face FA on the border brdr_ext (FIG. 3) of the entire outline of the first conductive layer P1cntr (FIG. 3).

[0113] The first etching 470 of the second conductive layer P2 again uses a photolithographed mask M70 defining the zones which are exposed or not to a directional etching, typically a dry etching of the plasma type.

[0114] Furthermore, the first etching 470 of the second conductive layer P2 is adapted to be selectively stopped by the dielectric layer ONO, in the portion of the high voltage transistors MOS HV-MV. During the etching 470, the dielectric layer ONO is located between the second conductive layer P2 and the gates of the high voltage transistors MOS HV-MV defined in the first conductive layer P1.

[0115] After the dry etching, a remainder of the dielectric layer ONO is typically present in the region of the high voltage transistors MOS HV-MV, and the remainder is removed by isotropic wet etching, typically by an acid bath of an adapted composition.

[0116] During wet etching, the low voltage dielectric layer GO is entirely covered in the region of the low voltage transistors MOS LV and in the region of the capacitive element CPP (GO).

[0117] FIG. 4H illustrates an etching step 480 adapted for high topologies allowing defining in a self-aligned manner floating gate and control gate stacks in the region of the memory cells NVMcell. A photolithographed mask M80 positions the stacks of the gate regions.

[0118] The other regions CP1P2, CPP, MOS HV-MV, MOS LV of the integrated circuit, which are in particular not adapted for a high-topology etching 480, are entirely covered by the mask M80.

[0119] FIG. 4I illustrates a second etching 490 of the second conductive layer P2, allowing defining the position and the shape of the gate structures of the low voltage transistors MOS LV.

[0120] Furthermore, the second etching 490 of the second conductive layer P2 allows forming an opening in the entire thickness of the second conductive layer P2 until reaching the first conductive layer P1, in the region of the capacitive element CPP (GO).

[0121] Again, the second etching 490 uses a photolithographed mask M90, defining the zones which are exposed or not to a directional etching.

[0122] The opening is formed to electrically separate a first portion P2int and a second portion P2ext of the second conductive layer P2. The first portion P2int is located on a central zone of the first conductive layer P1 so as to form a second armature, or electrode, of the capacitive element CPP. The second portion P2ext is located, on the one hand, on the first conductive layer P1 on the border of the entire outline of the first conductive layer brdr_int (FIG. 3), and on the other hand, on the front face FA on the border of the entire outline of the first conductive layer brdr_ext (FIG. 3).

[0123] Finally, a conventional formation (not represented) of contact pillars can be implemented in the different regions of the integrated circuit to connect the elements thus obtained to an interconnection network.

[0124] In particular, first metal contacts CT1P1 placed in the opening allow connecting the first armature P1 to a first electrode terminal of the capacitive element CPP (GO), and second metal contacts CT1P2 allow connecting the second portion P2ext of the second conductive layer P2 to the first terminal of the capacitive element CPP (GO), so as to obtain the previously described structure in relation to FIGS. 2 and 3.