Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The device may be, for example, a transistor or a capacitor. The device may be incorporated into a memory array. Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is formed over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.

A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.

Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

A memory unit, array and operation method thereof are provided. The memory unit includes at least one P-type driver having a first end coupled to a power source, a second end and a control end coupled to a word line; a memory cell having a first end coupled to the second end of the P-type driver, and a second end coupled to a bit line.

Provided is a dielectric thin film. The dielectric thin film includes: a plurality of ferroelectric domains including phonons having displacement in a direction of a first axis; and a plurality of spacers configured to block elastic interaction between the phonons, wherein the ferroelectric domains and the spacers are alternately and repeatedly arranged along a second axis which is perpendicular to the first axis.

A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.

A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.

Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells.