Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

A diffused resistor and method for forming a diffused resistor are provided. The diffused resistor comprises a substrate having a first conductivity type; a first well within the substrate having a second conductivity type; and a second well within the first well having the first conductivity type. The resistor further comprises a first and second contact for coupling the resistor to further circuitry. The first and second contacts are each coupled to both the first well and the second well.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

A semiconductor substrate of a first conductivity type having a first region of a second conductivity type formed in a surface thereof; an insulating film on the semiconductor substrate; a primary wiring line connected to the first region and configured to receive a voltage from outside; a plurality of diodes connected in series on the insulating film and having a spiral shape generally centering around the first region in a plan view, the diodes having one end of the series thereof connected to the primary wiring line and serving as a cathode; a resistor voltage divider having one end connected to another end of the series of diodes; a first connection wiring line connected to another end of the resistor voltage divider; and a second connection wiring line connected to a midpoint between the another end of the series of diodes and the another end of the resistor voltage divider.

One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.

A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

The present application relates to a pressure sensing device and a pressure sensing apparatus. The pressure sensing device (20) includes: one or more pressure sensing sheet (10), and a first substrate (22) configured for carrying the pressure sensing sheet (10); the pressure sensing sheet (10) is connected with the first substrate (22) by welding, and welding points are configured for transmitting a deformation and transmitting an electrical signal, and the pressure sensing sheet includes at least one semiconductor film (12), and a signal measurement circuit is integrated in the at least one semiconductor film (12), and the signal measurement circuit is configured for detecting an amount of the deformation and outputting the electrical signal that is able to be identified. Integrating the signal detection circuit in the semiconductor film (12) is greatly reduce the volume of the structure, which is beneficial to improve the integration degree of the product, and is beneficial to the miniaturization of the product.

An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.

An integrated device comprises an electrically conductive substrate having an upper surface comprising a recess and a lower surface for contacting the device, a multi-layer stack provided on the upper surface of the substrate and lining the recess, and an electrically conductive layer for contacting the device provided on the multi-layer stack. The multi-layer stack comprises a first, a second, a third and a fourth dielectric layer. Immediately adjacent dielectric layers have different bandgaps to trap charge carriers at respective interfaces between the dielectric layers during operation of the device.