A semiconductor device according to some implementations includes a main transistor, a peripheral circuit element connected to one end of the main transistor, and a Zener diode connected between the other end of the main transistor and the peripheral circuit element. The main transistor includes a main channel layer, a barrier layer disposed on the main channel layer, a main gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a main source electrode and a main drain electrode connected to the main channel layer. The peripheral circuit element includes a sub-channel layer connected to the main drain electrode and including a drift region with a two-dimensional electron gas, and a detection electrode disposed on the sub-channel layer, and the Zener diode is electrically connected between the detection electrode and the main source electrode.

A semiconductor device according to some implementations includes a main transistor, a peripheral circuit element connected to one end of the main transistor, and a Zener diode connected between the other end of the main transistor and the peripheral circuit element. The main transistor includes a main channel layer, a barrier layer disposed on the main channel layer, a main gate electrode disposed on the barrier layer, a gate semiconductor layer disposed between the barrier layer and the gate electrode, and a main source electrode and a main drain electrode connected to the main channel layer. The peripheral circuit element includes a sub-channel layer connected to the main drain electrode and including a drift region with a two-dimensional electron gas, and a detection electrode disposed on the sub-channel layer, and the Zener diode is electrically connected between the detection electrode and the main source electrode.

The present application discloses a strain sensing film, a pressure sensor, and a strain sensing system; the strain sensing film includes a semiconductor film, and by arranging a temperature sensor in the semiconductor film, the sensitivity of the strain sensing film is adjusted according to an effective gauge factor obtained from a calibration test and a correlation table reflecting a correlation between an effective gauge factor and a temperature, a better effective gauge factor compensation is achieved, a high sensitivity of the strain gauge of the semiconductor film can be fully utilized. The strain sensing film can be widely used in application scenarios that need to measure local strain or strain variation, force or force variation, pressure or pressure change, displacement, deformation, bending, or bending deformation.

The present application discloses a strain sensing film, a pressure sensor, and a strain sensing system; the strain sensing film includes a semiconductor film, and by arranging a temperature sensor in the semiconductor film, the sensitivity of the strain sensing film is adjusted according to an effective gauge factor obtained from a calibration test and a correlation table reflecting a correlation between an effective gauge factor and a temperature, a better effective gauge factor compensation is achieved, a high sensitivity of the strain gauge of the semiconductor film can be fully utilized. The strain sensing film can be widely used in application scenarios that need to measure local strain or strain variation, force or force variation, pressure or pressure change, displacement, deformation, bending, or bending deformation.

A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

Structures and related techniques for control of two-dimensional electron gas (2DEG) charge density in gallium nitride (GaN) devices are disclosed. In one aspect, a GaN device includes a compound semiconductor substrate, a source region formed in the compound semiconductor substrate, a drain region formed in the compound semiconductor substrate and separated from the source region, a 2DEG layer formed in the compound semiconductor substrate and extending between the source region and the drain region, a gate region formed on the compound semiconductor substrate and positioned between the source region and the drain region, and a plurality of isolated charge control structures disposed between the gate region and the drain region.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a first semiconductor layer, a second semiconductor layer, and a metal layer. The first semiconductor layer including a first material having a first bandgap. The second semiconductor layer is disposed on the first semiconductor layer, wherein the second semiconductor layer includes a second material having a second bandgap, and the second bandgap is different from the first bandgap. The metal layer overlaps the second semiconductor layer. An interface lattice mismatch (carrier channel) is formed between the first semiconductor layer and the second semiconductor layer.

The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.