A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

A driving circuit includes a first switching element operating in a turned-on state or a turned-off state depending on a control voltage; a second switching element operating complementarily to the first switching element depending on the control voltage; a constant voltage circuit unit turning on depending on a source-gate voltage of the first switching element to maintain a constant voltage; a current adjusting circuit operating in a turned-on state or a turned-off state depending on the control voltage, and adjusting an operating current flowing to a ground depending on a current control signal in the turned-on state of the current adjusting circuit; a current control circuit controlling the operating current by providing the current control signal to the current adjusting circuit in a turned-on state of the constant voltage circuit unit; and a signal transfer circuit providing the control voltage to a gate of the second switching element.

An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device.

An integrated circuit includes a drain in a substrate, wherein the drain comprising a doped drain well. The doped drain well includes a first zone, wherein the first zone has a first concentration of a first dopant; and a second zone, wherein the second zone has a second concentration of the first dopant, a top-most surface of the first zone is coplanar with a top-most surface of the second zone, and the first concentration is different from the second concentration. The integrated circuit further includes a gate electrode over the substrate, the gate electrode being separated from each of the first zone and the second zone in a direction parallel to a top surface of the substrate by a distance greater than 0.

A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

A semiconductor device comprising: a first electrode; a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; a fifth semiconductor region; an insulating portion that is provided between the second semiconductor region and the fifth semiconductor region and between the third semiconductor region and the fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; a second electrode; and a third electrode that is provided on the third semiconductor region and electrically connected to the third semiconductor region and the gate electrode.

An array structure of a single-poly nonvolatile memory includes a first MTP section, a first OTP section and a ROM section. The first MTP section includes a plurality of MTP cells, the first OTP section includes a plurality of OTP cells and the first ROM section includes a plurality of ROM cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section. The first ROM section is connected to a third word line, a third source line and the plurality of bit lines shared with the first MTP section.

RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.